2D Semiconductors Inch Forward

Key Takeaways:

• Diffusing oxygen into 2D materials can improve adhesion properties.
• Channel-last processes can preserve most of the traditional gate-all-around process flow.
• Dual-gate MoS₂ FETs with graphene contacts take advantage of layer transfer methods.

Transition metal dichalcogenides (TMDs) have come a long way since exfoliated flakes were the state of the art, but they still have a long way to go.

Materials like WSe₂ and MoS₂ are seen as potential replacements for silicon in highly scaled gate-all-around (GAA) transistors. They are two-dimensional, meaning they have no out-of-plane dangling bonds and are therefore less prone to interface scattering that degrades carrier mobility in very thin silicon channels.

However, these materials bring several serious challenges, too. Because they lack surface bonds, they are typically held to adjacent layers by relatively weak van der Waals forces. Adhesion is poor, and energy barriers at contacts can be high. Successful integration of TMDs is likely to require substantial changes to conventional CMOS processes.

Direct growth on silicon
One of the first and most urgent questions for TMD integration is material fabrication. TMD growth on substrates like sapphire is reasonably well established. Many studies of TMD transistors transfer these films to silicon wafers for further processing. Layer transfer techniques are difficult to scale, though. Commercial fabs would prefer direct growth on the final substrate, avoiding the complex handling, contamination risks, and relatively high costs of transferred films.

Unfortunately, chemical vapor deposition of TMDs often requires temperatures exceeding 600°C, which can degrade the underlying dielectric surface. TMDs themselves are also prone to plasma damage during subsequent processing. And thermal expansion mismatch can weaken their already poor adhesion, leading to delamination of the deposited film.

Researchers are addressing these issues in various ways. In work reported at December’s IEEE Electron Device Meeting, Huije Ryu and colleagues at Samsung deposited a thin passivating oxide on top of MoS₂ channels. This layer, they said, protects the 2D material and its interfaces from damage and contamination. At the same time, a sufficiently thin oxide layer is permeable to oxygen. By diffusing oxygen into the TMD material, the Samsung group selectively oxidized the edges of the channel regions. Strong bonds between the oxidized region, the substrate, and the channel helped prevent delamination. The same group also demonstrated a selective growth technique that reduced the time and thermal budget requirements for MoS₂ growth.[⁠1]

Sylvain Barraud and colleagues at CEA-Leti and Intel used a “channel-last” integration scheme that preserves most of the silicon-based GAA transistor process flow. They built a Si/SiGe multilayer stack and processed their devices through to the replacement metal gate and self-aligned contact etch steps. Then, as in a conventional GAA process, they removed the existing channels and filled them with ALD MoS₂ for nFETs and WSe₂ for pFETs, followed by the gate dielectric.[^⁠2]

Fig. 1: MoS₂ film deposited inside lateral cavities following silicon channel removal. Source: IEDM [2]

Making contact
Once the semiconductor channel is in place, interfaces with both the contact metals and the surrounding dielectrics are the next critical element of device performance. Since the channel is only one or two monolayers thick, surface damage and contamination can be catastrophic.

Quentin Smets and colleagues at imec followed TMD deposition with an aluminum oxide, then the HfO₂ dielectric. The aluminum oxide layer both protected their MoS₂ channels and served as an adhesion and seed layer for the HfO₂ deposition. An SiO₂ cap layer, deposited by PECVD at 400°C, partially crystallized the HfO₂, while the aluminum oxide was unaffected. As a result, the aluminum oxide etched much more rapidly. This selective etching technique enabled several process steps, including recess etching for contacts, a replacement-oxide process for the top gate, and removal of aluminum oxide from the gate stack.[^⁠3]

According to Terry Hung and colleagues at TSMC, contacts for PMOS TMD devices currently exhibit the largest gap between desired characteristics and demonstrated performance. While high-work-function metals can help reduce contact resistance, substitutional doping provides a much more robust, flexible solution. The TSMC group found that Pd/WSe₂ contacts had high levels of Se vacancies at the interface, which could be occupied by phosphorus dopants.[⁠4]

Complementary logic and heterogeneous CFETs
While direct growth device designs are making progress, complementary logic requires both n-type and p-type channel materials. Currently, WSe₂ is the leading p-type TMD semiconductor, while MoS₂ is the leading n-type material. Placing both materials on the same wafer by direct growth remains challenging. Peng Zhou and fellow researchers at Fudan University in Shanghai avoided the issue entirely by fabricating both enhancement-mode and depletion-mode devices using MoS₂ transistors with aluminum and gold gates. They demonstrated a functional microprocessor with nearly 6,000 transistors and four metal layers, grown on a sapphire substrate.[^⁠5]

Several groups are exploring layer-transfer approaches for heterogeneous vertical CFET structures. In addition to their work on the direct growth of MoS₂, Zhou’s group used a layer-transfer process to stack n-type MoS₂ transistors onto p-type SOI devices. The resulting CFET inverter outperformed both pure-silicon and 2D CFETs in terms of gain and power consumption.

At Purdue University, Jun Cai and colleagues sought to reduce parasitic capacitances in the source/drain overlap region. In silicon devices, the problem is solved by using dopants to reduce the resistance of the source/drain extension regions. Instead, the Purdue group transferred CVD-grown graphene to a prepared HfO₂ layer, using plasma etching to form contact extensions. Next, a CVD-grown MoS₂ monolayer was transferred and patterned to form the channel region.[^⁠6]

Fig. 2: Dual-gate MoS₂ FETs with graphene contact extensions. Schematic and false-colored SEM image. Source: IEDM [6]

Mechanics, heat, and the future
As researchers begin producing devices that resemble manufacturable structures, it becomes possible to evaluate their mechanical and thermal characteristics. While TMDs are quite strong as bulk materials, Hung pointed out that even strong materials may require additional support at monolayer thicknesses. Not surprisingly, they found that bilayers and trilayers of MoS₂ were more mechanically resilient than monolayers.

Heat dissipation is also a concern, according to Young Suh Song and colleagues at Stanford University. TMDs have very poor out-of-plane thermal conductivity and HfO₂ is a poor conductor of heat. Almost all heat transfer will occur through metallic contacts and the rest of the circuit wiring. In simulations, wrap-around contacts gave better thermal performance than edge contacts. Even so, TMDs with wrap-around contacts experienced a temperature rise three times that of comparable silicon devices. Intercalating lithium into multilayer TMD contacts gave better results, within 50% of their silicon-channel counterparts.[^⁠7]

Two-dimensional semiconductors first came on the scene as little more than research curiosities. They have since progressed to the point where they can be seriously considered as a successor material to silicon, but fundamental questions remain before they can actually step into a production role. Silicon CFETs pose substantial challenges, as well, but 2D semiconductors bring new materials, new processes, and many unknowns.

References

1. H. Ryu et al., “EOT-scaled 2D FETs on embedded bottom gates using direct channel growth on 200 mm wafers,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353501.
2. S. Barraud et al., “Novel channel-last integration of ALD MoS2 into stacked channel FETs on 300mm wafers,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353602.
3. Q. Smets et al., “Selective etch process for fab-compatible top contacts, replacement oxide, and interlayer removal in 2D FETs,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353796.
4. T. Y. T. Hung et al., “Mechanics of Integration and Component Performance Step-up for Nanosheet Transistors with Ultrathin 2D Channel,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353734.
5. P. Zhou et al., “Electronic Devices and System Integration in the Post-Moore Era,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353651.
6. J. Cai, et al., “First demonstration of DG monolayer MoS2 FETs with 0.3 nm-thin contact extensions achieving near immunity to SCEs at LCH=20 nm and gm=206 μS/μm,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353892.
7. 7. Y. S. Song et al., “First Comparative Thermal Evaluation of 2D Semiconductor vs. Silicon Nanosheet Transistors,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353799.

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