An Automated Method For Adding Resiliency To Mission-Critical SoC Designs


Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the Aerospace and Defense (A&D), cloud, automotive, robotics, medical, and Internet-of-Things (IoT) industries more resilient against random hardware failures that occur. Designing for reliable and resilient functionality doe... » read more

Week In Review: Auto, Security, Pervasive Computing


The European Parliament took a major step toward enacting the world’s first laws around the use of AI. Known as the AI Act, the draft law won a majority vote following two years of debate. If the proposed regulations pass the next hurdles, AI systems posing an unacceptable risk to human safety would be banned — along with “intrusive and discriminatory” uses of AI, including biometric su... » read more

Week In Review: Semiconductor Manufacturing, Test


Applied Materials sued its Chinese-owned rival, Mattson, over an alleged 14-month effort to steal valuable trade secrets, reports Bloomberg. In court filing, Applied Materials claimed that Mattson engaged in a spree of employee-poaching and covertly transferring semiconductor equipment designs. Global semiconductor materials revenue grew 8.9% to $72.7 billion in 2022, surpassing the previous... » read more

Week In Review: Design, Low Power


Intel released Tunnel Falls, its newest quantum research chip, to quantum computing researchers interested in using the 12-qubit silicon chip for their own experiments and research.  Intel is also providing the chips to research laboratories, with help from LQC (LPS Qubit Collaboratory) through the Army Research Office. The first labs to receive the chip are LPS, Sandia National Laboratories, ... » read more

Blog Review: June 14


Synopsys' Richard Solomon and Gary Ruggles examine the Compute Express Link (CXL) protocol and how it could unlock new ways of doing computing such as enabling efficient heterogeneous computing architectures, accelerating data-intensive workloads, and facilitating advanced real-time analytics. Cadence's Andre Baguenie explains how to convert an electrical signal to a logic value using the Ve... » read more

Programming Processors In Heterogeneous Architectures


Programming processors is becoming more complicated as more and different types of processing elements are included in the same architecture. While systems architects may revel in the number of options available for improving power, performance, and area, the challenge of programming functionality and making it all work together is turning out to be a major challenge. It involves multiple pr... » read more

Power/Performance Costs Of Securing Systems


For much of the chip industry, concerns about security are relatively new, but the requirement for protecting semiconductor devices is becoming pervasive. Unfortunately for many industries, that lesson has been learned the hard way. Security breaches have led to the loss of sensitive data, ransomware attacks that lock up data, theft of intellectual property or financial resources, and loss o... » read more

EDA’s Role Grows For Preventing And Identifying Failures


The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

Using Virtual Metal Fill To Solve Real Design Problems


People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those e... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies


An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

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