tag: Synopsys

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Will Wide I/O Reduce Cache?
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

Wide I/O’s Impact On Memory
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler Driven by the need to reduce power but increase bandwidth in smart phones and other mobile devices, system architects are grappling with new technologies to take system performance to the next level. Wide I/O, as well as some DDR technologies, are vying for center stage in tomorrow’s leading-edge mobile designs. “The big technological advancement that allows a ... » read more

Getting The Balance Right
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

3D Stacking: A Reality Check
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Blog Review: July 20
By Ed Sperling - 20 Jul, 2011 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected. Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting developme... » read more

Going With The Flow
By Ed Sperling - 15 Jul, 2011 - Comments: 0

It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows. Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included p... » read more

Different Ways To Boost Yield
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained. This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quick... » read more

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