SoC Design In 5 Years


By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

Virtual Prototyping Takes Off


By Ann Steffora Mutschler Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and eve... » read more

Too Soon For Wide I/O


By Ann Steffora Mutschler When 3D ICs are prevalent, Wide I/O is sure to be there. But where does the technology stand today? Considering the amount of buzz and hype, it would be easy believe it is being implemented in production designs today. Wide I/O is a very brute-force way of solving the problem of trying to get latency down with a high-speed memory interface, explained Navraj Nandra,... » read more

Managing Physical Effects


By Ann Steffora Mutschler Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower. Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die ... » read more

Low-Power Solutions At DAC


By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Experts At The Table: Power Budgeting


By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

One-On-One: Aart de Geus


Synopsys' CEO talks with Low-Power Engineering about the future of EDA, the changes in IP, stacked die and 20nm designs. [youtube vid=x9TKRC48OG0] » read more

Blog Review: May 25


By Ed Sperling Cadence’s Richard Goering follows Jim Hogan’s talk about the democratization of MEMS. This market is showing big gains lately, but to really release the emergency brake will require a different design approach. Mentor’s Robin Bornoff revs up the engine and turns on the neon underbody lighting in this look at the overclocking market, shifting effortlessly from cars to PC... » read more

Experts At The Table: Power Budgeting


Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul van Besouw, presi... » read more

Talk, Talk And More Talk


By Ed Sperling To anyone who owns a cell phone—and there are at least several billion people who claim that distinction these days—it’s not surprising that bad reception lowers battery life. More bars, while not the most accurate gauge of a signal, are at least an indication that you can extend the time between charges even if you’re watching streaming video. But work is under way a... » read more

← Older posts Newer posts →