tag: Synopsys

Experts At The Table: Power Budgeting
By Ed Sperling - 12 May, 2011 - Comments: 0

Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul van Besouw, presi... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 06 May, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 29 Apr, 2011 - Comments: 0

Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE: When we move t... » read more

‘What If’ In 3D
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling ‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node. When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design. ... » read more

EDA’s Big Challenge
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler It is not news to anyone that the growth rate of the EDA industry has been less than impressive, to put it politely. Traditional EDA implementation tools have hit commodity status and something’s got to change. Thankfully, there are a host of challenges coming in the form of system-level (and higher) design, not to mention what will be required for true 3D chips. ... » read more

SoC Ecosystems Become More Tightly Integrated
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target. Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platfo... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Power Issues In 3D
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantial... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 14 Apr, 2011 - Comments: 0

Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE: Power seems to... » read more

Verification At 28nm And Beyond
By Ed Sperling - 14 Apr, 2011 - Comments: 0

Low-Power Engineering looks at the challenges ahead in IC verification with Frank Schirrmeister of Synopsys, Ran Avinun of Cadence, Prakash Narain from Real Intent and Lauro Rizzatti from EVE. [youtube vid=bc5IhGrlJo4] » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy