Chip Industry Week In Review

By The SE Staff - 29 Sep, 2023 - Comments: 0

By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

Accelerating Analog Design Migration

By Yuval Shay - 28 Sep, 2023 - Comments: 0

Today’s electronic chips are commonly comprised of a mix of analog, RF, and digital components, with increasing functionalities, complexities, and numbers of transistors reaching the trillions. While the digital side of the house can take advantage of automated design implementation tools, the analog world has always been more about doing things manually and in a very “custom” way—which... » read more

Industry Pressure Grows For Simulating Systems Of Systems

By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

AI Drives Need For Optical Interconnects In Data Centers

By Karen Heyman - 28 Sep, 2023 - Comments: 0

An explosion of data, driven by more sensors everywhere and the inclusion of AI/ML in just about everything, is ratcheting up the pressure on data centers to leverage optical interconnects to speed up data throughput and reduce latency. Optical communication has been in use for several decades, starting with long-haul communications, and evolving from there to connect external storage to ser... » read more

What Happened To Portable Stimulus?

By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Universal Verification Methodology Coverage For Bluespec RISC-V Cores

By Synopsys - 27 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal Verification Methodology (UVM) standard. This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solu... » read more

Blog Review: September 27

By Jesse Allen - 27 Sep, 2023 - Comments: 0

Siemens' Dirk Hartmann examines how a continual improvement in predictive capability processing and algorithms enables the evolution of simulation performance and highlights two areas that underpin most simulation tools. Synopsys' Ian Land, Jason Niatas, and Marc Serughetti note that digital twins can be used from the chip level through sub-systems and up to the system level to examine perfo... » read more

ReRAM Seeks To Replace NOR

By Karen Heyman - 25 Sep, 2023 - Comments: 0

Resistive RAM is gaining renewed attention as demand for faster and cheaper non-volatile memory alternatives continues to grow, particularly in applications such as automotive. Embedded flash has long left designers wishing for better write speeds and lower energy consumption, but as the leading edge of that technology shrunk to 28nm, another problem arose. Manufacturing flash memory at thos... » read more

Chip Industry Week In Review

By The SE Staff - 22 Sep, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan The U.S. Department of Defense (DOD) announced $238 million in awards toward establishing eight regional innovation hubs under the CHIPS and Science Act. The hubs aim to accelerate hardware prototyping and "lab-to-fab" transition of semiconductor technologies for secure edge/IoT, 5G/6G, AI hardware, quantum technology, electromagnetic warfare, and ... » read more

When And Where To Implement AI/ML In Fabs

By Anne Meixner - 21 Sep, 2023 - Comments: 0

Deciphering complex interactions between variables is where machine learning and deep learning shine, but figuring out exactly how ML-based systems will be most useful is the job of engineers. The challenge is in pairing their domain expertise with available ML tools to maximize the value of both. This depends on sufficient quantities of good data, highly optimized algorithms, and proper tra... » read more

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tag: Synopsys

Chip Industry Week In Review

Accelerating Analog Design Migration

Industry Pressure Grows For Simulating Systems Of Systems

AI Drives Need For Optical Interconnects In Data Centers

What Happened To Portable Stimulus?

Universal Verification Methodology Coverage For Bluespec RISC-V Cores

Blog Review: September 27

ReRAM Seeks To Replace NOR

Chip Industry Week In Review

When And Where To Implement AI/ML In Fabs

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