What Next For OSATs

Semiconductor Engineering sat down to discuss IC-packaging and business trends with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation.

SE: What’s the outlook for the IC industry in 2017?

Wu: The overall landscape is positive. If you look at the semiconductor industry after 2010, the years from 2011 to 2016 basically operated between the 0% to 5% growth range. Sometimes, it was a little negative. Sometimes, it was slightly above 5%. But basically, the moving average for the last six years is between 0% to 5%. This year, everybody estimates that semiconductors are going to grow between 3% to 7%. So compared to 0% to 5%, you are like 2% to 3% above the moving average. That’s positive for the overall industry.

SE: OSATs provide third-party IC-packaging and test services. What’s the outlook for the OSAT industry in 2017?

Wu: In general, the OSAT growth tends to outpace semiconductors. So if we believe that semiconductors will grow 6% this year, then OSATs will outgrow that number.

SE: What else are you seeing?

Wu: We are seeing that the market conditions are continuing to improve, at least for the 2017 outlook. We are seeing strength in automotive, medical, IoT, PC and industrial. The biggest volume driver is still the handset.

SE: Some IDMs continue to invest in their own IC-packaging operations. Other IDMs are outsourcing more of their packaging production to the OSATs. Still others have sold their internal packaging operations to the OSATs as a means to cut costs. What’s happening here?

Wu: If you dissect the packaging and test business, you have OSATs and IDMs. The combined value of packaging between the OSATs and IDMs is moving in a steady state with the semiconductor industry. But the outsourcing portion of that is growing at a faster rate than the IDMs.

SE: What else?

Wu: In general, the IDMs are making relatively less investments in packaging. This has been the trend for the last 15 or 20 years.

SE: Let’s move to IC-packaging technology. The latest craze is fan-out wafer-level packaging. In fan-out, the interconnects are fanned-out in the package, enabling more I/Os. Fan-out isn’t new, right?

Wu: Fan-out was introduced in 2009. As a matter of fact, it was introduced by Infineon. ASE was the first one to collaborate with Infineon on 8-inch fan-out. From 2009 to 2016, there has been quite an evolution in the business environment.

SE: What do you mean?

Wu: 2016 was actually a milestone for the packaging industry. In 2016, the InFO from TSMC reconfirmed how fan-out can be adopted to improve the packaging part of the performance and the system-level performance.

SE: Apple is one of the first adopters for high-density fan-out. For Apple’s new iPhone 7, TSMC is making Apple’s A10 application processor. Based on a 16nm finFET process, Apple’s A10 is housed in TSMC’s fan-out packaging technology, dubbed Integrated Fan-Out (InFO). Why is that suddenly taking off?

Wu: Five years ago, TSMC started talking about a 2.5D technology called CoWoS (Chip-on-Wafer-on-Substrate). They also talked about 3D. That did not really ramp up in any volumes, mainly because the industry was not ready for those innovations at that time. Now, we are seeing InFO and fan-out getting traction. We are also seeing system-in-package getting traction. Why are they getting traction? It’s because the industry has developed to a point where the packaging portion of the heterogeneous integration can provide a bigger value to the overall semiconductor system. So, for the next five years, you will see more of a higher level of integration, whether it is for performance, form factor, power consumption or cost. You will see the packaging contribution becoming more prominent for the overall semiconductor system.

SE: Other smartphone OEMs are also looking at fan-out, but many are not quite ready to adopt it due to cost. Fan-out is still more expensive than the traditional solution for smartphones, namely package-on-package (PoP). In 2017, do you see more smartphone OEMs embracing fan-out?

Wu: It is difficult to say whether this will be the point or the day that fan-out will become overwhelmingly pervasive. We are not making that statement. However, you saw an industry milestone in 2009, which was the first launch of fan-out. Back in 2009, the industry was dealing with 65nm or 40nm. And today, the industry is dealing with 16nm/14nm moving to 10nm and 7nm. The 2017 landscape versus 2009 is quite different. Packaging technology has evolved. The chip-level cost, performance, form-factor requirements and the integration value part of it has also evolved. Regardless, I believe one statement is true—fan-out type of packaging is gaining more value percentage-wise for the overall semiconductor industry. If that’s the case, fan-out will get more attention now than it did in 2009.

Fig. 1: Integration roadmap for fan-out technologies. Source: Yole Développement

SE: Fan-out is going in several different directions, right?

Wu: The question is will the industry continue to evolve 12-inch fan-out into a panel format. In addition, there is not only a 2D format, but you also have to think about a 3D format. Or you might have a combination of all of the above.

SE: What are some of the key considerations in developing fan-out?

Wu: We need to be concerned about the cost and IP.

SE: Where is ASE taking fan-out?

Wu: If fan-out becomes a bigger reality, we would like to offer more of a full portfolio. That includes the traditional 8- and 12-inch fan-out, and also the small panel format, and possibly the large panel format. Of course, there is a lot of development dollars involved. We have to work with a lot of equipment suppliers to make this a reality.

SE: Last year, ASE invested $60 million in Deca, a developer of fan-out technology. (Deca is a subsidiary of Cypress.) What was that about?

Wu: The Deca investment is really more for the panel.

SE: Today, fan-out is based on a wafer-level format. In R&D, the industry is working on fan-out based on a panel format. The panel or square format enables more die, thereby lowering costs. What are the challenges?

Wu: Panel will be either be 300mm x 300mm square or 600mm x 600mm square. There are only a few companies in the world capable of doing panel. You must have a materials background, equipment automation support and IP. You also need to manage the dimensional stability and yield of the panel in a very large format.

SE: Today, high-density fan-out is targeted for high-end smartphones. But ASE and others want to make fan-out more pervasive in markets beyond the smartphone, right?

Wu: We are talking about having fan-out for every possible combination. This could involve power management, baseband, automotive, consumer and industrial.

SE: What else does fan-out bring to the party?

Wu: People do not have to depend solely on the SoC. Let’s say you are developing 7nm or 10nm chips. You can use a piece of 10nm or 7nm, and then combine it with the older-generation 28nm, 40nm and 65nm technologies. And then, we can use fan-out to make that a package-level SoC. That’s where the real economic value is.

SE: Where is 2.5D heading?

Wu: As we continue to evolve the technology at the system level, I can image that the optical guys will be very interested in using 2.5D. Maybe today’s 2.5D will evolve to fan-out. And 2.5D will be adopted by the future high end. That could be an optical link.

SE: Where is this all going in the future?

Wu: As the conditions continue to shift for the next 5 to 10 years, the question is how will the integrated packaging value play percentage-wise to the overall semiconductor system value? Then, you would ask—What exactly is an integrated package? It goes beyond fan-out. It goes beyond 2.5D or 3D. For this, you have to ask these questions—How do you form a more efficient integrated packaging system? How do the optical interconnects play into that role? How do the materials part of it play? How does the inductor, capacitor or embedded systems play in packaging? So you start asking a lot of materials and optical interconnect questions.

SE: So there are a lot of pieces involved, right?

Wu: We are developing all of the building blocks. And it’s almost like we are developing a highway and a high-speed railroad. We don’t know what type of traffic will go through it. But once the infrastructure is ready, the industry will always find a requirement for it.

SE: Let’s move to the business side. Today, there are more than 100 OSATs in the market. At the same time, the OSAT industry is consolidating. Will we see more consolidation in 2017?

Wu: In packaging, the consolidation has really just started. You have seen the acquisition of STATS ChipPAC by JCET. That was the biggest one until we saw Amkor’s acquisition of J-Devices. Now, you see ASE and SPIL. The consolidation will continue.

SE: The larger OSATs are developing more complex package types, such as 2.5D/3D and fan-out. Therefore, it requires more R&D dollars to develop these technologies. So, the OSATs may need to pool their resources and consolidate, right?

Wu: Consolidation is mainly driven by the economic benefits. You are looking to get a bigger critical mass such that you can exercise economies of scale.

SE: What else is fueling the consolidation?

Wu: The customers are consolidating. That will continue in the semiconductor industry. That will drive the supply chain to have more consolidation, especially in packaging.

SE: China is making a big play in packaging, right?

Wu: Generally, in China, the OSATs are growing at a faster pace. This is mainly driven by the national policy or China’s drive towards semiconductors.

SE: In 2014, China launched an initiative called the “National Guideline for Development of the IC Industry.” One goal is to accelerate China’s technology base. The other goal is to become more self-sufficient in terms of making its own chips. As a result, China is advancing its domestic chip and packaging segments. Any thoughts?

Wu: There is a national appetite and drive to have more of a relative self-sufficient supply of semiconductors in China. That drive at the national level, which cascades across the whole country, is enormous. The question is, can they do it? And the other question is which area will they expand into first? To answer those two questions, you have to assume they will do it. So which segment will come out first in China? Maybe memory. Maybe design houses. Maybe design tools. Maybe equipment. Maybe materials. The whole thing is linked together. Regardless, whatever we know how to do today, we have to assume in three to five years’ time, they will know how to do it. They might not know how to do it better. But they will know how to do it cheaper and produce more of it. You have to make that assumption. Any other assumption, I don’t think we are doing our fiduciary duty.

SE: How will the industry respond?

Wu: The next question is what are we going to do about it? We are driving next-generation fan-out and 2.5D. We are driving the materials building blocks. We continue to sharpen our wirebond technology and CapEx know-how. We are increasing our economic scale. We continue to drive R&D for the next-generation of requirements. We are doing everything we can possibly do to anticipate that China will come up strong.

Related Stories
OSAT Biz: Growth And Challenges
Dizzying number of options emerge, but cost remains key factor.
Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Making 2.5D, Fan-Outs Cheaper
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.