Why Indium Oxide Chips Are Getting So Much Attention

Key Takeaways

• Their low leakage is of interest for memory applications, particularly capacitor-less gain cell designs;
• They can be deposited over large areas using low-temperature processes, a very desirable characteristic for BEOL integration, and
• The variety of compositions available gives designers many options to achieve the specific properties they need. Indium tin oxide (ITO), In₂O₃, indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and even indium gallium zinc tin oxide (IGZTO) have all demonstrated promising results in at least some cases

As the semiconductor industry gets serious about monolithic 3D integration, indium-based oxide semiconductors are drawing more and more attention.

The variety of options allows designers to adjust the composition to balance the tradeoff between transition voltage (V_t) and mobility. For example, a group at Purdue University found that increasing the gallium content in indium gallium oxide decreased carrier mobility. Keeping gallium content low while doping with fluorine gave better results. They achieved an on/off current ratio of about 10¹¹, with a subthreshold swing of 85 mV/dec.[^⁠1]

In top-gated and dual-gated ITO devices, atomic-layer deposition of the top dielectric often dopes the channel, leading to a negative threshold voltage. In work presented at December’s IEEE Electron Device Meeting, Dylan Matthews and colleagues at Duke University replaced the conventional HfO₂ dielectric with ZrO₂, achieving a positive threshold voltage at temperatures up to 125°C. Though they did not actually fabricate short-channel devices, they projected an on current of 1.25mA/micron in 20nm channels, with a subthreshold swing below 100 mV/dec.[^⁠2]

Bias temperature instability, positive and negative
Unfortunately, indium oxides are amorphous under normal conditions. As such, they have inherently disordered structures with many electrical states. They are prone to bias temperature instability (BTI) and have more complex BTI behavior than usually seen in silicon. The reason researchers are considering so many different indium-based oxides is partly because metal cations can help stabilize oxygen vacancy behavior.

Oxygen vacancies, in turn, are a major factor in BTI behavior. While oxide semiconductors are well-established in display applications, CMOS-compatible integration schemes are relatively unexplored. The Duke University researchers also evaluated the contributions of RF power, deposition pressure, and oxygen annealing conditions to ITO channel composition. Annealing in a 90:10 Ar:O₂ atmosphere gave the best results, which they attributed to an optimal oxygen vacancy concentration.

Depending on the material and the bias conditions, BTI can cause a V_t shift in either a positive or negative direction. Shifts are especially damaging in memory applications, where a change of even a few millivolts can lead to data loss. Understanding BTI behavior is an urgent challenge for indium-based semiconductors.

Where does the hydrogen go?
Next to oxygen vacancies, hydrogen doping is an especially important factor. It appears to accumulate in the transistor’s HfO₂ dielectric layer, probably as a byproduct of HfO₂ deposition. While annealing in forming gas (a hydrogen/nitrogen mixture) is the last step in a conventional CMOS process — serving to passivate defects and heal plasma damage — work from a group of researchers from Georgia Tech, Applied Materials, and Samsung, among others, found little difference in BTI behavior between nitrogen and forming gas anneals.[^⁠3]

In dual-gated ITO devices, Md Sazzadur Rahman and colleagues at Duke University found that hydrogen near the top gate served to passivate oxygen vacancies, forming In-H-In bonds. Near the bottom gate, hydrogen bonded with free oxygen to form OH covalent bonds.[⁠4]

Earlier work on IGZO FETs by Gan Liu and colleagues at the University of Singapore found that, under positive (DC) stress, hydrogen passivates electron traps in the channel, increasing carrier concentration and reducing V_t. That is, hydrogen reduces the impact of electron traps. In Liu’s work, the most stable PBTI behavior was achieved at a channel thickness of about 4nm.

Electron trapping effects dominate in thinner layers, hydrogen effects in thicker layers.[^⁠5] Thinner channels are desirable to minimize short-channel effects as the channel length scales down. More recent work by Liu’s team on IGZTO FETs found that PBTI behavior was also temperature-dependent. At low temperatures, electron trapping dominated, leading to a positive V_t shift. At higher temperatures (about 107°C in their work), hydrogen effects dominated, and the V_t shift was negative.[⁠6]

Under negative bias conditions, though, the effect of hydrogen was complicated. First, electrons from the gate can combine with H⁺ ions (protons) in the dielectric, then diffuse into the channel. At the same time, H⁺ ions already present in the channel can diffuse into the dielectric, increasing positive charge accumulation there. The negative V_t shift observed under negative bias conditions appears to result from the net movement of H⁺ ions due to these effects.

Conditions in real devices more closely resemble AC stress, rather than DC stress. The AC frequency determines the length of the recovery interval between cycles. In negative bias AC stress, Liu said, the net effect was negligible, with little change in V_t over time. On the other hand, positively-biased devices saw a gradual negative V_t shift with the number of cycles. Generally speaking, indium-based FETs appear to be more reliable under AC conditions than DC results might indicate.

Fig. 1: Under positive bias conditions, AC stress gradually shifts the transition voltage in a negative direction. Under negative bias conditions, the net effect of AC stress is negligible. Source: IEEE IEDM [6]

Accelerated testing, or maybe not
Among the unusual behaviors observed in indium-based transistors, the change in hydrogen behavior at elevated temperatures is particularly worrisome. It calls into question the effectiveness of accelerated reliability testing. Rahman’s work found that the V_t shift under positive stress was lower at elevated temperatures (85 and 125°C), but recovery was slower. That is different behavior than seen in silicon devices. Elevated temperatures appear to anneal out shallow traps near the HfO₂/ITO interface, while at the same time generating new deep traps.

Defect annealing explains the reduced V_t shift, while deep defects would explain slower recovery times. Once the devices returned to room temperature, though, both effects disappear and the devices return to their unstressed behavior.

Fig. 2: Changes in trap distribution in ITO FETs with temperature. Traps marked with ‘x’ are present at room temperature and annealed at high temperatures. Circled traps are new defects that appear at elevated temperatures. IEEE IEDM [4]

Looking toward commercialization
From a research perspective, the complexity of indium-based oxide semiconductor systems is fascinating. Labs can customize devices to explore whatever aspect of the interaction between oxygen, hydrogen, and metal composition they want to explore.

As Samsung, Applied Materials, and other companies sponsoring this research look to commercial applications, though, they will need materials that can reliably deliver the same behavior across thousands of wafers and millions of transistors. Identifying such materials is still a work in progress.

References

1. J. Zhang et al., “Fluorine Anion-Doped Ultra-Thin InGaO Transistors Overcoming Mobility-Stability Trade-off,” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413810.
2. D. Matthews et al., “First Demonstration of Positive Threshold in Dual-Gated ITO FETs with ZrO2 Dielectric,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353482.
3. Y.-H. Kuo et al., “Experiments and Modeling of Defect Dynamics and BTI in Doped In2O3 TFTs Undergoing Densification during 400 °C Post-BEOL Forming Gas Annealing (FGA),” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353585.
4. M. S. Rahman et al., “Can High-Temperature PBTI Testing Predict Dual-Gated ITO FET Long-term Reliability?” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353802.
5. G. Liu et al., “Unveiling the Influence of Channel Thickness on PBTI and LFN in Sub-10 nm-thick IGZO FETs: A Holistic Perspective for Advancing Oxide Semiconductor Devices,” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413735.
6. G. Liu et al., “Revealing the Impact of Hydrogen (H) on NBTI/PBTI of IGZTO FETs Under DC and AC Stress: Deep Dive into H Dynamics and Advanced Modeling,” 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4, doi: 10.1109/IEDM50854.2024.10873553.

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