Accellera Updates UVM Standard

New verification standard readied for submission to IEEE; 90-day public comment period begins.


Accellera uncorked its backward-compatible UVM 1.2 standard, which fixes dozens of bugs, including sequences for run-time phasing and support for multithreading.

“We’ve solved more than a dozen incompatibilities and improved overall productivity,” said Intel’s Thomas Alsop, who serves as co-chair of the UVM (Universal Verification Methodology) working group. “This is a major release. We’re now taking the 1.2 implementation and converting it to the IEEE format. That includes a 90-day review period.”

Industry comments will be accepted until Oct. 1 and can be added online by clicking here.

This is the first of three major efforts under way regarding UVM. The multi-language working group is developing a way of allowing different languages, such as C and Specman, to be simulated together. The goal is to simplify the integration of IP developed in different languages. The spec is due for release sometime this quarter.

A second working group is adding SystemC support for UVM, including a full SystemC version of UVM. Given that UVM is essential a set of libraries around languages, that would allow it to support both SystemVerilog and SystemC. The spec is due out by year’s end.

Accellera also said it is launching two new DVCon shows, one in Munich from Oct. 14 to 15, and another in Bangalore in September. And the standards group has released a new version of Verilog-AMS 2.4, which extends compact modeling and behavior modeling by defining how analog behavior interacts with event-based functionality. This release had been expected for some time.