What Transistors Will Look Like At 5nm

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner.

The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node.

But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. Then, there are several technical and economic roadblocks. And even if 5nm happens, it’s likely that only a few companies will be able to afford it.

“My current assumption is that 5nm will happen, but it won’t hit high-volume manufacturing until after 2020,” said Bob Johnson, an analyst at Gartner. “If I were to guess, I’d say 2021 to 2022.”

At 5nm, it will cost $500 million or more to design a “reasonably complex SoC,” Johnson said. In comparison, it will cost $271 million to design a 7nm SoC, which is about 9 times the cost for a 28nm planar device, according to Gartner.

For those who can afford to migrate to 5nm, there are two main transistor contenders at this node—the finFET and the lateral gate-all-around FET. Gate-all-around (GAA), sometimes called the lateral nanowire FET, is a finFET on its side with a gate wrapped around it.

In fact, momentum is building for gate-all-around in the industry. “GAA transistors provide better electrostatics than finFETs, which should allow for some additional gate length scaling,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel.

But the jury is still out on the feasibility of gate-all-around, prompting the industry to consider finFETs at 5nm. Regardless of the architecture, the challenge is to develop 5nm designs that go beyond niche-oriented markets at the high end. Otherwise, the return-on-investment is questionable. “I know there will be a 5nm generation, covering a range of product types,” Bohr said.

For now, gate-all-around is generating the most buzz, although this technology presents several challenges in the fab. Making the patterns, gates, nanowires and interconnects are all challenging. In addition, process control could be a nightmare. And, of course, the ability to make gate-all-around FETs in a cost-effective manner is key.

To help the industry gain some insights into gate-all-around FETs, Semiconductor Engineering has taken a look at the basic process flow and the challenges with this technology. Additionally, there is a discussion on futuristic devices, such as complementary FETs and vertical nanowires.

What is gate-all-around?
Today, chipmakers are ramping up finFETs, but not everyone is at the leading edge. In logic, for example, the sweet spot is still at the 40nm and 28nm planar nodes.

Many foundries, in fact, have recently “experienced a surge in 28nm business, especially from communication customers,” said Po Wen Yen, chief executive of United Microelectronics Corp. (UMC), during a recent conference call. For example, UMC’s 28nm fab utilization rate is more than 90% in Q3 of 2016, up from around 70% in the previous period, Yen said.

The market also is heating up at the high end. Starting at 22nm and 16nm/14nm, chipmakers migrated from planar devices to finFET transistors. The reason is that finFETs help solve the short-channel effects in planar devices. In finFETs, the control of the current is accomplished by wrapping around a gate on each of the three sides of a fin.

Eventually, the finFET runs into several issues, though. “Post-7nm, we do see some challenges,” said Kelvin Low, senior director of foundry marketing for Samsung. “We have enjoyed increased Vcc (supply voltage) performance gain every time we scale down the CPP (contacted poly pitch). We think we are at a cliff right now at 7nm CPP dimensions. So something has to be done with different device structures and different stress techniques to address this trend.”

Moreover, the copper interconnects—those tiny wiring schemes in devices—are becoming more compact at each node, causing an increase in the resistance-capacitance (RC) delay in chips. “We expect RC delay to go up significantly,” Low said.

Generally, though, the finFET can be extended to 5nm, although that may require new channel materials. One idea is to inject silicon germanium (SiGe) for pMOS.

“This will allow you to get more performance without having to scale the (fin) height,” said Mike Chudzik, senior director of strategic planning at Applied Materials. “Actually, it doesn’t allow you to scale the gate length. But it enables improved mobility.”

But once the fin width reaches around 5nm, the finFET runs out of steam. “You can scale your fin,” Chudzik said. “Then, all of a sudden, you get quantum confinement. Your bandgap goes up as the fins get very, very narrow. And then your threshold voltage shifts up.”

That’s why chipmakers are interested in gate-all-around. “(Gate-all- around is) much more complicated than what we’re doing now, but it’s a natural progression of the finFET,” said Dave Hemker, senior vice president and chief technology officer at Lam Research.

On the surface, gate-all-around resembles a MOSFET, where a gate is sandwiched between the source and a drain. In addition, gate-all-around also consists of a finFET. But unlike today’s finFETs, where the fins are in a vertical fashion, the finFET is turned on its side in gate-all-around.

Gate-all-around FET also incorporates three or more nanowires. The nanowires, which form the channels, are suspended and run from the source to the drain. The dimensions are staggering. For example, IMEC recently demonstrated a gate-all-around FET in which each nanowire is 8nm in diameter.

A high-k/metal-gate structure, which controls the flow of the current, fills the gap between the source and drain.

Still, the question is clear—Why go to gate-all-around? “Actually, I suggest it’s not particularly better in electrostatics,” Applied’s Chudzik said. “You want to go to gate-all-around because of variability and variability performance.”

Others agreed. “It’s not like from finFET to gate-all-around that you get a huge advantage,” said David Fried, chief technology officer at Coventor. “You get a little bit of extra electrostatic control of the transistor.”

The big benefit, according to Fried, is the ability is to scale the gate length. “So, you get the full wrap around and a little bit of electrostatic control,” he said. “Gate-all-around also says you will get some gate scaling.”

So, which architecture—the finFET or gate-all-around—is superior for 5nm? It’s unclear right now, as each technology has some advantages and disadvantages.

Chipmakers face some tough decisions. “There will be two or three or more finFET nodes, and it will really be a question of whether you’re changing the material, or whether you go to horizontal nanowire,” Lam’s Hemker said. “The transistor hasn’t changed, but (the question is) can you get the I^on/I^off with the feature size that you need?”

In addition, there are other options on the table at 5nm, such as 2.5D stacked die and 3D devices, among others.

EPFL’s conceptual image of a gate-all-around FET.

Making gate-all-around
There are several ways to make gate-all-around FETs. In one simple flow, a chipmaker first decides on the channel materials for the pFET and nFET structures. The options for pFET are silicon, germanium (Ge) or SiGe. For the nFET, silicon, SiGe, Ge or a III-V material could be used.

Ge and III-V have higher mobility properties than silicon, but these exotic materials suffer from defect and reliability issues. So, perhaps a simpler approach is to use silicon and/or SiGe. “Silicon germanium is a more benign material than jumping to germanium and III-V,” said Dan Mocuta, director of logic devices and integration at Imec.

Case in point: Imec’s gate-all-around process starts by forming a super-lattice structure on top of a bulk CMOS substrate. Imec’s super-lattice, square-shaped structure consists of a stack of alternating layers of SiGe and silicon. Ideally, a stack would consist of three layers of SiGe and three layers of silicon.

Making a (flat) finFET
Once the super-lattice stack is developed, the finFET is formed. In gate-all-around, the fin is on its side. Still, the process steps follow a traditional finFET flow. Using traditional doping techniques from an ion implanter, a source and drain are formed on top of the super-lattice square stack. A source is formed on one end of the stack, while the drain is developed on the other end.

Following that step, the top of the super-lattice structure is patterned in the form of the letter “H”. Then, after several lithography and etch steps, the structure then resembles the letter “H”. The H-like figure is lying flat.

The two tall structures (I I) in the H-like figure at each side represent the source and drain. The middle portion (-) is part of the fin.

This process presents some challenges. For the patterning steps, there are two lithographic options today—extreme ultraviolet (EUV) lithography and 193nm immersion. Both EUV and immersion would also require a multiple patterning scheme at 5nm.

Chipmakers could use both technologies at 5nm. Regardless, they want EUV for 7nm and/or 5nm to simplify the patterning steps in the flow. “Without EUV, the mask layers could explode,” Samsung’s Low said. “With EUV, we are talking about less mask layers.”

EUV, however, is still not in production amid a number of challenges with the power source, photoresists and the mask infrastructure.

Today, ASML is shipping the latest version of its EUV scanner—the NXE:3350B. The 13.5nm wavelength tool has a numerical aperture of 0.33 and a resolution of 16nm half-pitch.

ASML also is upgrading the scanner from an 80-watt to a 125-watt source. This, in turn, will boost the throughputs to 85 wafers per hour (wph), up from 55 to 65 wph. In addition, ASML is readying another version of its EUV scanner line—the NXE:3400B. Targeted for 5nm, the NXE:3400B has a 13nm resolution.

The company also plans to ship a power source at around 200 watts (or more) by this year or next. But as before, chipmakers want EUV scanners with a 250-watt source to put the technology in mass production. This would enable a throughput of 125 wph.

“We still need a lot more work to be done to get the throughput for EUV lithography where we need it to be,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.

In addition, chipmakers also are struggling to obtain EUV resists that enable patterns below 30nm half-pitch. “If we have resist sensitivities of 20 millijoules per centimeter square, we can get close to cost parity with immersion triple patterning,” Levinson said.

“Based on the data we’ve seen to date, we don’t think we are going to be able to have sufficiently low line edge roughness with 20 millijoule per centimeter square resists. But perhaps for the 7nm node, 30 millijoules per centimeter square might be possible. That doesn’t bring us to cost parity with immersion triple patterning. But given some of the other advantages with EUV lithography, particularly the cycle time, this still may be a true value proposition and justify the use of EUV lithography at 7nm,” he said.

Making nanowires
The next step is perhaps the most difficult in gate-all-around—making the nanowires.

After the patterning steps, the structure resembles an H-like figure. As stated above, the two tall structures (I I) represent the source and drain. The middle portion (-) is where you make the nanowires.

For this step, Imec and others have developed a replacement metal gate process. Initially, the middle portion is a super-lattice structure, which consists of an alternating layer of SiGe and silicon.

Using a replacement process, the goal is to remove the SiGe layers in the alternating stack. This, in turn, leaves the silicon layers with a space in between them. Basically, each silicon layer forms the basis of a nanowire. And each nanowire has been strained with SiGe to boost the channel mobility.

Ideally, a device would have three separate nanowires. Each nanowire runs in a horizontal direction. And each nanowire is suspended and runs from the source to the drain.

Basically, the three nanowires are placed on top of each other (top, middle and bottom). The nanowires are separated by a space and are not touching each other.

Typically, chipmakers use an etch tool to remove materials in this gate replacement process. But traditional etchers won’t necessarily work at the required dimensions for gate-all-around.

The challenge is to remove the SiGe in the gaps that measure 15 angstroms or less. (One angstrom equals 0.1nm.) The other challenge is to remove the SiGe without disturbing the other parts of the device.

For this process, chipmakers would use a next-generation etch technology called atomic layer etch (ALE), which selectively and precisely removes targeted materials at the atomic scale. In theory, ALE can remove the SiGe between the silicon layers without causing damage or leaving residue.

“The idea is to remove the silicon germanium selectively to the silicon,” said Matt Cogorno, global product manager at Applied Materials. “So with this selective etch process, you create these nanowires.”

There are some challenges, however. “There is a parasitic channel formed under the nanowires. You have to find a way to cut off that leakage through that parasitic channel,” Imec’s Mocuta said. “The way we do that is what we call ground plane doping. We dope the region before we deposit this super-lattice structure. That cuts off the leakage and improves the sub-threshold slope.”

Imec’s gate-all around FET with two stacked nanowires.

Gates and interconnects
Now, the device requires a gate. Using atomic layer deposition (ALD), high-k/metal-gate materials are deposited in the tiny gap between the source and drain. So, in effect, the gate surrounds each of the nanowires.

“There are some serious deposition challenges here,” Coventor’s Fried said. “In a finFET, you look down into a gate trench. You see the fin there. You deposit materials everywhere. You have to worry about the sidewalls of the fin a little bit. But you can see where you are depositing.”

It’s a different story for gate-all-around. “Now, when I look down, I see these wires. I need to deposit materials all the way around them in places I can’t see. And I need to get a high-quality conformal coating,” Fried said.

Others agreed. “You don’t have any line of sight at all. Not only are you coating around the wire, but you have to coat on the underside of the wire. It’s really dependent on chemistries that work perfectly,” said Mohith Verghese, director of global product marketing at ASM International (ASMI).

The solution? “We will see a re-emergence of thermal ALD. It’s completely chemistry dependent,” Verghese said. Generally, thermal ALD involves a binary process with two reactants—A and B. The first reactant, A, is pumped into the ALD chamber. The wafer is processed and then the chemistries are purged. Then, the second reactant, B, undergoes the same step.

Ultimately, though, the interconnects could be the biggest roadblock at 5nm. To solve the RC delay issues, chipmakers will need new breakthroughs. “It’s a difficult problem,” Lam’s Hemker said. “You will need to attack this problem on all fronts. It’s going to take a comprehensive solution of materials, equipment, integration schemes and device layouts.”

What’s next?
In R&D, chipmakers are also looking at 3nm and beyond, although it’s unclear if these nodes will ever happen.

For 3nm, the industry is exploring horizontal gate-all-around FETs and vertical nanowire FETs. “We’re doing work with some universities on vertical nanowires, too, which are great if you can actually make them and make contacts to them. Now you’ve decoupled transistor performance from the density. You have to shrink them down and make them smaller and smaller, so leakage goes up every generation. This way the leakage is dependent on how tall is the wire, and the packing density is the diameter. So now they’re more independent. You still have to etch these things and fabricate them and there’s a lot of work that has to be done,” Hemker said.

In addition, the complementary FET is also generating some buzz. This device resembles a horizontal gate-all-around. One nanowire is an nFET, while the next one is a pFET. And so on. “You isolate these devices and stack them in the third dimension,” Coventor’s Fried said. “That would be a paradigm shift. It’s a complete shift in getting circuit density. That’s really challenging.”

Related Stories
Will 5nm Happen?
5nm Fab Challenges