Imec’s process technology and logic devices guru talks about 7nm and 5nm parasitics, new materials and transistors, and where are the biggest unknowns.
Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec.
SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm?
Thean: 10nm is on its way. We will see risk production in the 2016 time frame. So everybody is now busy with 7nm, or starting to do 7nm. Risk production for 7nm will start sometime in 2018, meaning most of the research has to be done by the 2016 time frame. That’s a rough timeline. You can see how hectic that might be. So, in a two-year time frame, we will be locking down 7nm research in terms of the options.
SE: When does the R&D need to be done for a node?
Thean: It’s typically two years before risk production. And then within that two-year span, people go through the development phase, where they will get the technology ready for production. It doesn’t pertain to anybody specific, but this is the general cadence today.
SE: What is Imec working on in logic?
Thean: We are now working on 7nm and 5nm. Our research is moving towards 5nm.
SE: What are some of the big challenges today?
Thean: FinFETs are fairly successful. You see a lot of people adopting it, but the parasitics for finFETs are a big challenge. You have contact resistance and coupling capacitance. We are trying to tackle some of these problems. We’ve also talked about next-generation transistor technologies like gate-all-around nanowires. Those are also the kind of technologies we are working on. It’s not easy making those types of things. It’s a magnitude of order harder than finFETs. Yet, the value proposition is there.
SE: Some say the finFET could run out of gas when the fin width goes below 5nm. Is that the case and what’s next?
Thean: Today, the fin thickness for finFETs is around 7nm to 8nm. You can maybe go to 5nm at the next node. At 5nm and beyond, we will need to look at more exotic channel materials. We will also look at nanowire architectures. We are evaluating vertical-based circuits, in which the way to achieve the electrostatics could be a little easier, as compared to lateral devices. But they have their own set of challenges in terms of layouts and circuit architectures.
SE: What are the challenges to bring III-V materials into the channels?
Thean: The challenges are still the materials and the gate stack. III-V doesn’t enjoy the same benefits as silicon in terms of the amount of time that people have been working on it. So it suffers from a lack of maturity. III-V does bring some performance benefits, however. The key question is bandgap. It is a very narrow bandgap material. So if you want to actually run it at the operating voltages that we have today, you might get a fair amount of band-to-band tunneling. So that gives you an increase in leakage. So that’s something we need to understand. Second, the gate-stack reliability is a little bit more challenging than silicon. That needs a little bit more work. The third thing is scalability. When you squeeze a III-V channel down, you do see a quantization effect. There is a penalty to pay there. So those three things mean that a III-V device may have to be in a unique architecture.
SE: When will III-V channel materials appear in IC designs?
Thean: We are still working on it. But we are working on it from a 5nm standpoint rather than 7nm. As I mentioned before, the time is getting close for 7nm. The research for 7nm must be done by the 2016 time frame.
SE: The industry is talking about germanium and/or silicon germanium in the channels at 10nm/7nm. What are the challenges?
Thean: Germanium and III-V are both being worked on. Germanium, being a group IV material, is conducive to co-integration with silicon. Silicon germanium could come in earlier. Silicon germanium is a little easier to handle than germanium. But if you want to get a boost in silicon germanium, you would have to bump up the germanium content and then you start to approach pure germanium. Germanium also has a very narrow bandgap. It also suffers from the same problem in terms of band-to-band leakage. That means it has to be co-integrated with something else.
SE: Will the industry ever adopt III-V materials for the channels?
Thean: The verdict is still out. We are still working on it. To be honest, we’ve made tremendous progress in III-V and combining it with silicon. It opens up a lot of different possibilities. For instance, you might integrate devices that typically are better made in III-V than silicon. There is optoelectronics, for example. At Imec, we are working on monolithic III-V lasers co-integrated on silicon. But will III-V ever take a finFET form? We don’t know quite yet. But the process capability we’ve developed could get us there.
SE: Some believe the finFET could extend to 7nm. Are there other options at 7nm and/or 5nm?
Thean: By 7nm, the electrostatics are severely challenged. That means in order to get to the same electrostatics we have today, we have to do something fundamentally different in the channel. That determines the architecture of the device. That’s why we are looking at nanowires as an option. What is that nanowire option? Is it pure silicon? Is it silicon-germanium? Is it germanium or III-V? We are still looking at that. Today, if you look at the readiness, silicon is no problem. Silicon-germanium is not a big problem. The pieces are there. In terms of germanium for the PFET, we have most of the pieces as well. There are still a lot of questions for III-V, but there is a big value proposition in terms of mobility. That’s where things stand as we see it today. So there is still a lot of work to do.
SE: What’s the roadmap for nanowire FETs?
Thean: Today, we are looking at lateral structures first. It looks like a fin from the top, but it is segmented into gate-all-around segments. With that, you could at least maintain the level of sub-threshold swing that we see today in finFETs, but at a smaller gate length.
SE: Imec is also working on vertical nanowires, right?
Thean: We are still evaluating it for 5nm and beyond. That’s a more disruptive implementation. It does allow you to scale more easily. With vertical nanowires, III-V could come in as an attractive option.
SE: What about tunnel FETs?
Thean: That work is still fairly vibrant. People are making good progress. Some of these things still have a lot of fundamental issues. But the desire to seek out a device with a steep slope is clear. The concept looks very revolutionary, but the technology is fairly evolutionary. It may require a III-V selective process. The question is how you combine them with different materials.
SE: Imec is also working on quantum-well finFETs, right?
Thean: That’s like a silicon-germanium channel device. That could be a quantum-well finFET device. It’s a class of devices, which has a heterogeneous channel.
SE: Is Imec working on FD-SOI?
Thean: We don’t have a big scale effort on it. However, it’s a very sound approach. It’s a good option for people that are going for low-power types of applications.
SE: What will likely happen at 5nm and beyond?
Thean: We are approaching the point where lateral nanowire structures may run out of steam. So that’s why we are looking at more exotic devices. For example, the TFET will get more attention there. Even some of the beyond-CMOS types of activities will start to come in.
SE: Does this involve the 2D materials?
Thean: Yes, like the diselenides. These are the transition-metal dichalcogenides materials. They are interesting because they have intrinsically a wider bandgap. They lend themselves to be transistor-like channel materials. We are looking at those things. The idea is can we use these materials to make devices that we can combine with conventional CMOS to add functionality, and not necessarily as a replacement for CMOS.
SE: Let’s get back to 7nm. What are the other challenges?
Thean: As we work on 7nm in research, the circuits are getting very congested. So even if you could pack the transistors in, it’s very difficult to connect them together. Each transistor, small as they are, requires at least three to four connections to it. You can imagine the jungle of wires you have to connect them. So that congestion is becoming a huge issue. So that’s why people are looking at novel device architectures that will reduce device count.
Thean: Through-silicon vias allow for stacking at the functional block level. That should take off. Eventually, people will start to look at stacking beyond the block level, such as the transistor level. If you try to shrink it down to the transistor level, then you have this sequential or monolithic 3D processing. That technology is not clearly mapped out yet. It’s not clear how it should be done, but it’s an active field of research.
SE: What about EUV?
Thean: EUV is needed. It would make life a lot easier. We need any help we can get, especially with patterning. Things are difficult enough.
SE: What’s missing in terms of tool technologies in the fab?
Thean: The new stuff we are hoping to get someday is being able to selectively control surfaces, such as to grow and remove materials. The reason for that is clear. You are seeing more and more non-planar structures. But most of the processing is still based on planar processing. So if you have ways to access the structures from the sides, that would help a lot. That could become a focus for materials and tool suppliers going forward.
SE: Can you elaborate?
Thean: Today, selective epitaxy is a form of that technique. But we need more than just forming crystalline material. We need this type of technology for dielectrics, metals and different things.