Using PCI Express L1 Sub-states To Minimize Power Consumption In Advanced Process Nodes

The major sources of Internet traffic are shifting from wired to wireless and mobile devices. With the growing regulatory requirements and increased consumer pressure for more power-efficient products, designers need to better understand and optimize the power consumption of battery-operated devices.

Power consumption of a portable device widely varies based on the user’s behavior and applications. The two distinctive power states of a fully powered mobile product are the active (a.k.a. dynamic) and idle (a.k.a. static) states. In an active state, either the device is continuously interfaced by the end user, or one or more applications are in active use. In an idle state, the end user is not actively engaged and the applications are in standby or sleep mode. A device consumes significantly lower power in an idle state than in an active state, and the idle state is considered to be the low-power mode of a device.

Even with the considerable variations in the use patterns of mobile device users, on average over 50 percent of the total device power is consumed when the device is in its idle state, pointing to the need for a power-optimized idle state.

In addition to the growing need for lower power idle states in mobile devices, device data rate requirements are increasing. To accommodate the need for higher bandwidth in mobile devices, device architects are migrating from PCIe 2.0’s 5 Gbps data rates to PCIe 3.0’s 8 Gbps data rates as well as from 65/45nm nodes to 28nm and smaller nodes. The combination of higher data rates in smaller process technologies reduces active power consumption but dramatically increases idle power consumption, as shown in Figure 1.

Figure 1: Normalized active and idle power for a single lane PCIe SerDes across process nodes

Smaller CMOS geometries enable designers to reduce active power as threshold voltage decreases, SoC area shrinks, and supply voltages go down. SoC designers can use techniques such as dynamic voltage scaling, clock gating, power gating, and channel optimized equalization circuitry to further optimize the overall active power of a device.

However, smaller geometries with lower threshold voltages have much higher leakage currents that inversely impact the mobile device’s idle power consumption. To make matters worse, high-speed mixed-signal designs with low supply voltages in small process geometries may require the use of lower threshold voltage devices that increase leakage power across process, voltage and temperature (PVT) (Figure 2). Aggressive power management strategies, such the use of higher threshold voltage devices (HVt), power islands with power switches, static voltage scaling, and the use of enhanced link power management techniques defined by PCI Express (PCIe), can reduce idle power to near zero.

Figure 2: Normalized leakage power for single lane PCIe SerDes across process and PVT corners, using standard threshold voltages. Leakage can be minimized with the use of HVt.

PCI Express specification power states
The PCIe defined four link power state levels that are software controlled: fully active state (L0), electrical idle or standby state (L0s), L1 (lower power standby/slumber state), L2 (low power sleep state), and L3 (link Off state).

As links transition from L0 to L3 states, both power saving and exit latencies increase. In the L0 state, the link is fully active in its ready mode and consumes the maximum active power. During short intervals of logical idle in absence of link activities, the link may transition into an L0s state with very low exit latencies (several hundred nanoseconds) for a small power reduction.

In the L1 state, all supplies and all reference clock components are fully active except as permitted by the clock power management (using CLKREQ#) when enabled. When the optional internal PLL is off or on, Tx and Rx may be off or idle, and the common mode keeper remains active. Depending on the number of optional active devices in L1 state, power savings in the L1 standby mode can be limited and does not meet the requirements of mobile market as intended, even though the exit latencies of L1 state could be in the order of microseconds under certain conditions.

In the L2 sleep state, all clocks and main power supplies are turned off, providing the highest idle state power savings. However, exit latencies are very long, in the order of milliseconds, and not acceptable; therefore, the L2 power state is not commonly used in mobile applications.

To reduce power consumption in the L1 idle state with reasonable exit latency targets and without impacting the overall performance of the PCIe link states, PCI-SIG defined two new sub-states as part of the L1 link state. L1 sub-states L1.1 and L1.2 utilize a per-link bi-directional sideband clock request signal, CLKREQ# that is required by both ports on the two ends of a link. If both ends of the link are not L1 sub-state capable and enabled, then the link may only operate in the legacy L1 power state.

Internal PLLs no longer have an option to be on and should be turned off in both L1.1 and L1.2, as reference clock inputs are not required in L1 sub-states. Similarly, both the Tx and Rx are turned off and are not required to detect electrical idle in these sub-states. The main difference between L1.1 and L1.2 is the common mode voltage status, as it is maintained in the L1.1 and is turned off in L1.2 sub-state. Therefore, because of the common mode restoration time, exit latency of L1.2 is much longer than L1.1. Table 1 summarizes the target power and exit latencies for each of the power sub-states.

Table 1: Link and PHY/PIPE Power Sub-states in Idle States

As PCIe-based devices adopt the newly defined L1 sub-states in their next-generation designs, there will be dramatic reduction in idle power consumption, where 10’s of milliwatts of power in an L1 state will be reduced by orders of magnitude in L1.1 or L1.2 sub-states. With the addition of power islands and power gating with power switches, the overall power consumption of a device can be reduced and the operating life of a battery charge can be extended, with minimum impact on exit latencies.

Synopsys’ silicon-proven DesignWare® PCIe PHY IP, along with controller and verification IP, enable designers to implement a PCIe solution that meets both the active and low idle power requirements of today’s power sensitive markets, especially mobile and battery operated applications.