Second of two parts: Interconnects and patterning become the big bottlenecks at future nodes; stacked die emerge as a way to sidestep major technology issues.
Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm.
Technically, it’s possible to manufacture the transistor portions of the technology, sometimes called the front-end-of-the-line (FEOL). But at 7nm/5nm, what could hold up the scaling train, and Moore’s Law, is the backend-of-the-line (BEOL). The BEOL is where the interconnects are formed within a device. Interconnects, the tiny wiring schemes in devices, are becoming more compact at each node, causing a resistance-capacitance (RC) delay in chips.
In fact, the BEOL is lagging behind in the manufacturing flow, which, in turn, could cause the RC delay to escalate exponentially at each node. “We are able to cram more than 1,000 interconnects in the width of a human hair,” said Kavita Shah, global product manager at Applied Materials. “But starting this year, we are seeing our end customers look at new materials for the backend. They are concerned that the backend is not keeping up.”
The industry has found ways to mitigate the RC delay at least down to the 10nm node. But at 7nm and beyond, chipmakers are searching for new tool and material breakthroughs. And there is little or no consensus in the arena. “You will need to make a change at 7nm,” said Zsolt Tokei, program director for interconnects at IMEC. “At 7nm, the market is wide open.”
At 7nm, the industry is exploring several new materials for traditional dual damascene structures, such as cobalt (Co), manganese (Mn) and ruthenium (Ru). Then, in addition to these materials, the industry is looking at two exotic technologies, carbon nanotubes and graphene, for the interconnect at 5nm.
The industry also may need to think outside the box, as there are still several integration issues with these next-generation materials. To circumvent the RC delay problem, chipmakers must continue to pursue the vertical path. In this segment, there are several options on the table, such as stacked 2.5D/3D chips, monolithic 3D and vertical nanowires.
Litho and material issues
In a device, there are two types of BEOL interconnect wires, intermediate and global. Intermediate wires provide the lower-level connections in a device. As before, the problems associated with RC delay reside with the global wires, which connect the intermediate layers. Adding to the complexity is that chipmakers have inserted another wiring hierarchy starting at 20nm. The scheme, dubbed the middle-of-the-line (MOL), involves the local interconnects in a design.
In the BEOL, there are many process steps, which fall into two categories—patterning and the dual damascene process. Initially, in the flow, each level of a given chip structure must be patterned to create the wiring schemes. For this, chipmakers use 193nm immersion and multiple patterning in both the FEOL and BEOL.
BEOL patterning is arguably more problematic and costly at each node. “If you look at it today, the metal layers and contact/wire layers are among the most critical ones,” said Kurt Ronse, director of advanced patterning at Imec. “They are also probably the most difficult thing for 193nm lithography to scale up to. That’s where EUV could come in and take over.”
At 7nm and beyond, chipmakers would prefer to use extreme ultraviolet (EUV) lithography for BEOL patterning. EUV could bring the BEOL back into the single exposure era. And if EUV could achieve a throughput of 150 wafers an hour, BEOL costs could fall by almost 30%, according to Imec.
But EUV is late and not ready for production. If EUV misses 7nm, chipmakers must extend today’s lithographic solutions. “The lack of EUV lithography requires pitch splitting, which greatly drives up the cost as more wiring levels will be required,” said Daniel Edelstein, an IBM fellow and manager of BEOL technology strategy at IBM.
Meanwhile, after a given level is pattered, the device goes through the copper dual damascene process. This process involves three main parts—metallization; low-k dielectrics; and the capping layer. In the metallization step, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.
Then, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier. The barrier layer is coated over by a copper seed barrier. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing.
“In today’s interconnects, we start to see some challenges, such as high current densities,” Applied’s Shah said. “As this current density goes up, other secondary electrical effects start to dominate. In order to address the electrical aspects of interconnect technology, we are beginning to see the need for new materials.”
In fact, Applied recently rolled out a new tool that brings Co into the flow. Using chemical vapor deposition (CVD), Co is used for the liner instead of Ta. Using PVD in the same tool, TaN is still utilized for the barrier. “The idea of using a cobalt liner layer is to promote continuity for the copper seed,” Shah said.
For the liner/barrier, Co and TaN will likely scale to 10nm. Then what? At 7nm, the industry is evaluating Co and Ru for the liner. Each material has tradeoffs. “Since the 65nm node, people have been talking about ruthenium,” Shah said. “The biggest benefit of ruthenium is that it has even better properties versus cobalt in terms of acting as a good layer for copper. The other benefit with ruthenium is that it allows copper to reflow. So you can envision that you can fill these interconnects using PVD.”
Ru also has some drawbacks. For one, Ru is difficult to polish. “Ruthenium is not manufacturing friendly,” she said. “You might actually trap metallic ruthenium all along your low-k and have a lot of leakage.”
For the barrier, meanwhile, there are also various options at 7nm—TaN, Ru alloys and manganese-based self-formed barriers (SFB). “TaN continues to stay around,” she said. “Manganese is promising, but we don’t have all of the data.”
In the lab, Applied Materials and Imec recently described a CVD process that enables 2nm Mn-based SFBs. The results were promising, as the material had 14% lower copper resistivity than conventional PVD-based barriers. On the other hand, IBM and GlobalFoundries recently showed different data—PVD-based TaN could extend beyond 10nm.
Meanwhile, the industry is exploring other approaches and for good reason—the evolutionary solutions may fail or could become too expensive. In one novel approach at 7nm, the industry is talking about self-aligned via (SAV) schemes, which may address the problem of via-to-metal shorting at tight pitches. The main challenge is the misalignment of the SAVs themselves.
Looking to solve the problem, Lam Research and United Microelectronics Corp. (UMC) recently described a SAV scheme for sub-90nm BEOL pitches. In the flow, a thin TiN metal hardmask is used for trench pattern definition. The interconnect vias are patterned using a tri-layer resist mask. Then, the vias are self-aligned to the under-layer trench lines.
In addition, the industry is also looking at carbon nanotubes and graphene as interconnect options at 5nm and beyond. Both technologies have exceptional electrical properties, but they are expensive and difficult to integrate in a CMOS flow.
Taking a step to solve the issues, Imec has developed a 200mm fab flow, which enables 150nm vertical carbon nanotube interconnects. In the flow, carbon nanotubes are grown using CVD. Then, a conformal oxide encapsulation is used to protect the structures during planarization. The carbon nanotube tips are cleaned and then moved to a metallization process using a single damascene approach.
“A carbon nanotube-to-metal contact resistance of 76Ω and lower was obtained for 150nm diameter contacts,” said Marleen van der Veen, a researcher at Imec. “The result is that our carbon nanotube interconnects have ballistic transport over 24nm, which is five times longer than reported so far.”
For 5nm, Imec is also developing a vertical nanowire transistor, which may use conventional materials or carbon nanotubes as the interconnects. In fact, by 5nm or sooner, the industry may have no choice but to go vertical, as interconnect technology in evolutionary devices could simply stop scaling.
Besides the vertical nanowire, there are other futuristic options. One technology, monolithic 3D integration, involves a process of stacking, aligning and connecting leading-edge transistors on top of each other to form a monolithic 3D chip. Using standard vias, monolithic 3D ICs are said to provide 10,000 times more connections at smaller feature sizes than stacked 2.5D/3D TSV technology.
CEA-Leti, one of the main drivers of the technology, recently outlined the challenges with monolithic 3D. The top transistor thermal budget must be limited to preserve the bottom FET. In other words, the industry must find activation techniques below 600°C. With that in mind, CEA-Leti is exploring several technology options, such as laser anneal tools. Tools with low wavelength of 308nm with short pulse durations are promising. At present, though, solid phase epitaxy is the most promising technology.
Meanwhile, there are also more conventional approaches, namely the old standby—stacked die. In fact, the resistivity problems in planar devices have recently fueled the development of stacked 2.5D/3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D chips.
But advanced 2.5D/3D chip stacking still has several challenges. Claiming to make a major breakthrough in the arena, GlobalFoundries recently described a via-middle TSV integration scheme for the sub-28nm nodes, which uses a new local interconnect technology. The approach mitigates the high thermal budgets required for the FEOL, thereby subjecting the TSVs to lower thermal budgets.
At 28nm, the first BEOL metal is placed on top of the TSV, resulting in a one-level contact. In the new scheme for 20nm and beyond, the TSV is electrically connected to the M1 layer using V0 vias. This, in turn, creates a two-level contact scheme. “How you integrate TSVs at 28nm is different than what you do at other nodes,” said Rama Alapati, director of package architecture and customer technology at GlobalFoundries. “What you need to worry about changes significantly, such as electromigration and stress migration.”
With this and other breakthroughs, 2.5D/3D chips could soon become a mainstream technology. “The technology is not the bottleneck anymore,” Alapati said. “Cost might be an issue. But when we go into volume production, cost will eventually go down.”
Needless to say, the industry is still sorting out the options for 7nm and 5nm. Chipmakers may need to take two different paths, including the traditional and the 2.5D/3D road. “RC is king,” said Applied’s Shah. “At the end of the day, you need to meet your RC target.”
To view part 1 of this series, click here.