Solving Today’s Toughest Test Challenges: A New Era Of Engineering Productivity


Today’s test engineers face unprecedented demands as semiconductor designs grow more complex and product cycles accelerate. Advanced packaging, chiplet architectures, and AI accelerators are reshaping the landscape, yet engineering resources remain fixed. Traditional approaches to scaling productivity by adding headcount no longer apply. While cost of test is always a consideration, ensuri... » read more

In-System Test For AI Data Centers


Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Interconnect Innovations In High Bandwidth Memory: Part 2


By Damon Tsai, Woo Young Han, and Tim Kryman Interconnect technology in high bandwidth memory (HBM) is at a fork in the road. One direction leads to tried-and-true microbump technology, and the other leads to a compelling alternative, hybrid bonding. Both technologies are evolving to address the stringent requirements of next generation HBM in pursuit of increased I/O density supporting high... » read more

Expanding The Scope Of Testing In Complex Systems


Semiconductor devices now anchor the world’s most demanding infrastructures—from hyperscale data centers to advanced automotive platforms and industrial control systems. At scale, even rare faults can have significant cumulative impact, and the downstream consequences of failure extend far beyond a single board or rack. Unplanned outages translate into lost revenue, contractual penalties, f... » read more

The Future Of Semiconductor Manufacturing: How AI And Industry Collaboration Are Reshaping The Value Chain


The semiconductor industry stands at an inflection point. As Moore's Law scaling becomes increasingly challenging and system complexity explodes through advanced packaging and chiplet-based architectures, the traditional siloed approach to manufacturing must give way to an unprecedented level of industry collaboration. This transformation, driven by the convergence of artificial intelligence, c... » read more

Enhancing Test Socket Performance Through Application-Specific Validation And System-Level Per-Pin OQC


As semiconductor devices continue to advance, the demand for reliable, high-performance test sockets has never been greater. Yet, traditional socket design validation methods—such as per-pin characterization and generic housing evaluations—often fall short of reflecting true application specific system-level performance. This gap between lab measurements and real-world application not only ... » read more

Critical Optimization Factors For GenAI Chipmakers


Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

New Frontiers In Fault Detection And Classification


IC manufacturers are increasingly relying on intelligent data processing to prevent downtime, improve yields, and reduce scrap. They are integrating that with fault detection and classification (FDC) to trace faults to their cause. Today’s FDC systems feature better sensors, variability control, and both predictive and prescriptive modeling. In the future, FDC will enable real-time decisio... » read more

Revolutionizing Chip Testing: Navigating Bottlenecks


In today's rapidly evolving semiconductor landscape, System-on-Chips (SoCs) are becoming increasingly complex, integrating multiple processing cores, specialized accelerators and vast memory arrays. This escalating complexity, while enabling incredible functionality, presents significant challenges for Design-for-Test (DFT) engineers. Ensuring the thorough and efficient testing of these intrica... » read more

Metrology’s Growing Role In Reducing False Defects


When a good die fails test and gets scrapped, often no one notices, because false failures look identical to real ones. Yet across the industry, these phantom defects are quietly eroding yield, inflating test costs, and masking the true health of manufacturing processes. At advanced nodes and in heterogeneous packaging, where margins are already razor-thin, even minor variations in contact r... » read more

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