category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Hybrid Approach Emerges For Edge/Cloud Inspection Of Chips
By Anne Meixner - 14 Oct, 2025 - Comments: 0

An explosion in data from inspection images and metrology measurements is creating a confusing set of demands for chipmakers and their equipment vendors. On one hand they need the massive storage and compute resources of the cloud to utilize AI/ML-based models, but they also need the faster response time of the edge to make adjustments at the tool level. Balancing these requirements is a mas... » read more

Rethinking Security In Semiconductor Testing: Why Containment Is The New Imperative
By Arik Peltz - 14 Oct, 2025 - Comments: 0

It’s nearly impossible to keep up with the headlines without stumbling upon another major cybersecurity incident. According to recent reports, 2024 witnessed a staggering 5.5 billion breaches globally. In the United States alone, the average cost of a single data breach clocked in at $9.36 million—slightly lower than 2023’s figure, but still a significant hit for any organization. On a gl... » read more

Enabling In-Line Process Control for Hybrid Bonding Applications
By Onto Innovation - 14 Oct, 2025 - Comments: 0

As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad ... » read more

Silicon Lifecycle Management
By Ed Sperling - 22 Sep, 2025 - Comments: 0

How chips are used is changing, and so are the requirements. In the past, markets were largely segmented by application, which determined how chips were designed. High-performance processors went into notebook computers, low-power chipsets were deployed in mobile devices, and complex SoCs and advanced packages were used in data centers. But with the spread of AI everywhere, traditional segmenta... » read more

Interconnect Innovations In High Bandwidth Memory: Part 1
By Damon Tsai - 09 Sep, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman The demand for high bandwidth memory (HBM) is accelerating across the semiconductor industry, driven by boundary-pushing artificial intelligence, high-performance computing, and advanced graphics. These technologies require access to vast datasets, which in turn increases the need for memory solutions that combine speed, density, and power efficie... » read more

Case Study: Production Yield And Throughput Improvement Using The Known Good Socket Analysis
By Jesse Ko - 09 Sep, 2025 - Comments: 0

The test sockets, which are crucial components that directly interface with semiconductor IC packages, have a profound impact on device testing performance. Pins with high CRES not only cause false failures in the test but also lower bin grading results, which in turn increase the manufacturing cost due to reduced production performance. The ever-increasing demand driven by high-performance com... » read more

Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
By John Kibarian - 09 Sep, 2025 - Comments: 1

The semiconductor industry has always been a story of constant evolution, titans rising and falling, technologies advancing at breakneck speed, and billions of dollars riding on the difference between first and second place. And today, AI, geopolitics and the increased need for collaboration are reshaping the chip industry once again. After more than three decades navigating the complexities... » read more

Making The Most of Test Resources
By Laura Peters - 09 Sep, 2025 - Comments: 0

Semiconductor testing is undergoing multiple paradigm changes at once with the common goals of producing more known good die per month with low test cost. Achieving these goals requires a delicate balance between yield, quality, and test times. There are multiple ways to go about making better use of existing resources, many of which involve an increasing use of design for test (DFT) methods... » read more

The Hidden Cost Of Contact Resistance
By Gregory Haley - 09 Sep, 2025 - Comments: 1

Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Data Feed Forward And How It Works: Part 2
By Roberto Colecchia - 09 Sep, 2025 - Comments: 0

As chiplets and advanced packaging redefine semiconductor architecture, managing complexity isn’t just about the silicon—it’s about the data. Modern multi-die packages often contain components from different vendors, integrated in 2.5D or 3D configurations. Each die brings its own risks, and diagnosing issues after assembly is increasingly difficult—especially when data isn’t share... » read more

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