category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Implementing High-Density-Advanced Packaging For OSATs And Foundries
By Mentor, a Siemens Business - 05 Jun, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Testing IoT Devices
By Jeff Dorsch - 05 Jun, 2017 - Comments: 3

Internet of Things devices present new challenges in testing. Some devices can be tested the same way as standard semiconductors are now tested, but others call for different approaches. Microcontrollers and other chips that go into safety-critical applications — medical devices, military/aerospace systems, and automotive electronics — need their own kind of testing to make sure they wil... » read more

Leasing and Rental in T&M
By Jeff Dorsch - 05 Jun, 2017 - Comments: 0

Buying a high-end oscilloscope or a brand-new logic analyzer may be a tall order financially for small companies. In such cases, leasing or renting an expensive test instrument can be an affordable alternative. Having reliable test and measurement equipment is vital to product development in electronics. National Instruments has built a billion-dollar business on offering instrument hardware... » read more

Advanced Packaging Goes Mainstream
By Ed Sperling - 08 May, 2017 - Comments: 0

The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century. This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and ... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package
By STATS ChipPAC - 08 May, 2017 - Comments: 0

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

The Future of Testing
By Jeff Dorsch - 08 May, 2017 - Comments: 0

In our previous test blog posts, we looked at the history of automated test equipment for semiconductors and for printed circuit boards. This month, we look ahead to the test technologies that are emerging. The chip ATE field has essentially boiled down to Advantest, Teradyne, and Xcerra (LTX-Credence), while the board test market is dominated by Teradyne and Keysight Technologies (formerly ... » read more

Wireless Test: Too Many Protocols
By Jeff Dorsch - 08 May, 2017 - Comments: 0

Testing wireless communications is getting far more difficult as more markets begin adding wireless communications and standards groups push to improve the speed, power and security of existing protocols. There is already a long list of protocols, and it's growing further as new communications technologies are added into the mix. With the addition of 5G, the new 802.11ax standard, and other ... » read more

Finally, Realizing The Full Benefits Of Parallel Site-To-Site (S2S) Testing
By Guy Cortez - 08 May, 2017 - Comments: 0

A very common and well-known practice by manufacturers during the IC test process is to test as many of the device die or packaged parts as possible in parallel (i.e. sites) during wafer sort and final test in order to increase test time efficiency and lower overall test costs. The constraints that typically restrict how many test sites can be used at any given time are the design I/O and capac... » read more

Wirebond Technology Rolls On
By Mark LaPedus - 08 May, 2017 - Comments: 2

Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

Intel Inside The Package
By Ed Sperling - 08 May, 2017 - Comments: 1

Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

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