category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Power-Aware Test: Addressing Power Challenges In DFT And Test
By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach
By Vamsi Velidandla - 10 Aug, 2021 - Comments: 0

By Vamsi Velidandla, John Hauck, Zhuo Chen, Joshua Frederick, and Zhihui Jiao The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin... » read more

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Better Optimization For Many-Core AI Chips
By Richard Oxland - 10 Aug, 2021 - Comments: 0

The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

Who Owns In-Chip Monitoring Data?
By Bryon Moyer - 10 Aug, 2021 - Comments: 1

In-chip monitors provide unprecedented visibility into the inner workings of complex integrated circuits for everything from process control to fine binning, preventive system maintenance, and failure analysis. But there may be many consumers of different slices of the data at very different phases of the chip lifecycle, raising questions about who controls and owns all of that data. The ans... » read more

Multi-Layer Deep Data Performance Monitoring And Optimization
By proteanTecs - 10 Aug, 2021 - Comments: 0

Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementa... » read more

Characterization Of Micro-Bumps For 3DIC Wafer Acceptance Tests
By FormFactor - 10 Aug, 2021 - Comments: 0

The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

SLT Enables Test Content To Shift Right
By Dave Armstrong - 10 Aug, 2021 - Comments: 0

By Dave Armstrong, Davette Berry, and Craig Snyder Increasing device complexity and the continuing drive for higher levels of quality are fostering a reconsideration of test strategies. To be effective, test engineers must choose how to optimally deploy test content, from wafer probing to system-level test (SLT). A March 2019 TestConX presentation1 outlines how test content is typically allo... » read more

Residual Stress With EIGER2 R 500K
By Bruker - 10 Aug, 2021 - Comments: 0

Many manufacturing processes leave residual stresses which can affect the performance of manufactured components. Compressive stress can be engineered into a metal coating to resist crack propagation, while tensile stress can be exploited to enhance conductivity in semiconductors. Strained materials exhibit changes in atomic spacing which can be detected by X-ray diffraction (XRD) and related t... » read more

Production Testing For Silicon Photonics Wafers
By David Viera - 10 Aug, 2021 - Comments: 0

Worldwide data centers and networks for communications currently consume about 8% of the Earth’s total energy produced. To meet the increasing demands for cloud storage, computing, and various emerging applications such as artificial intelligence, genomics revolution, and video transcoding, hyperscale data centers are being built around the world at an accelerated pace, with analysts predicti... » read more

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