Equipment Suppliers Brace For GaN Market Explosion

A huge GaN market is opening up, driven by consumer devices and the need for greater energy efficiency across many applications. Suppliers are ready, but to fully compete with SiC in high-voltage automotive applications will require further technological developments in power GaN (gallium nitride).

Still, the 2020s mark a very high-growth phase for GaN markets. Revenues in the power GaN market are growing at a 59% CAGR (2021 to 2027), on target for hitting $2 billion in five years (per Yole Group’s Power GaN 2022 report).

Leading the high-growth path is the consumer segment, which for power GaN alone should flirt with the billion-dollar mark by 2027, followed by datacom and automotive/mobility. The RF GaN market is no slouch, either. Over a similar period, that market should reach $2.5 billion, with nothing but high growth beyond, predicts Yole.

That means a lot of pressure on IDMs and fabs — and on their equipment suppliers. “Those are massive markets,” notes Victor Veliadis, executive director and CTO of the PowerAmerica consortium. “But that mass market pressure is going to put a lot of financial pressure on. So they’re going to have pressure to have higher throughput, higher yield, bigger wafers.”

Fortunately, GaN manufacturing can largely be done by the same equipment used for silicon CMOS. The exceptions are the critical epitaxy steps at the onset, which will become even more critical as power GaN reaches for ever higher voltages. However, beyond epi, leading equipment suppliers are working ever more closely with their customers to respond to burgeoning demand.

Fig. 1: Yole Group predicts a CAGR of over 59% for revenue in power GaN device markets between 2021 and 2027, reaching $2 billion. Source: Yole Group

Process points
GaN starts with epi. What varies is the kind of wafers on which the epitaxy is grown. Those starting wafers can be silicon, silicon carbide, sapphire, or even bulk GaN. It depends on the design choices and the target applications. But whatever the starting substrate, GaN epitaxy is complex. Because the crystalline structure of the starting wafers is different from the ultimate top GaN layer (unless, of course, you’re starting with bulk GaN wafers, which are just a few inches in diameter, which makes them less attractive), buffer layers are needed to make the crystalline transition.

GaN epi is applied by metal-organic CVD (MOCVD). “When looking at GaN HEMT manufacturing, MOCVD tools are masterpieces. For that, there are several providers, namely Aixtron, Veeco, and Taiyo Nippon Sanso,” noted Taha Ayari, technology and market analyst in Yole’s Compound Semiconductor and Emerging Substrates group. “These tools need to satisfy several criteria such as throughput, thickness and composition uniformity, reproducibility, and yield control. Etching tools are also important since clean sidewalls and smooth surfaces are needed. Key suppliers of etching tools are SPTS (a KLA company), Lam Research, and Oxford Instruments, amongst many others. Generally speaking, equipment suppliers need to work hand-in-hand with their clients to better understand the requirements of the GaN manufacturing process.”

The explosion of the power GaN market is driven by adoption in the consumer phone charger market, where mass production and higher volumes with lower prices are required. This implies transitioning to larger wafer sizes from the mainstream 6-inch silicon substrates. Today, some players already have 200mm (8-inch) GaN-on-Si fabs (Innoscience and X-Fab), or they are moving to 200mm (Infineon, STMicroelectronics, Nexperia, BelGaN, and TSMC) in the coming years, said Ezgi Dogmus, team lead analyst in Yole’s Power & Wireless Division.

On the foundry side, X-Fab got a very early start. “As the first pure-play foundry, we offer customers the capability to process their highly efficient, high-voltage power devices on 200-mm-GaN-on-silicon wafers using our European CMOS production facility in Dresden, Germany,” said Agnes Jahnke, X-Fab product marketing manager for SiC and GaN. “There is no specific or dedicated tool for the GaN wafers. All equipment is set up to handle both wafer materials (silicon and GaN-on-Si).

However, it’s not easy to process GaN-on-silicon wafers in a running CMOS fab. “It comes with some restrictions — for example, no noble metals or wafers thicker than 1mm can be used,” said Jahnke. “And a lot of challenges related to material stress, breakage probability, contamination levels, defectivity, and process integration need to be tackled. But on the other hand, the good electrical performance, larger wafer area, and higher yield brings significant advantages to customers so they can compete with the IDMs and other GaN players in the market.”

X-Fab outsources the starting epitaxy to international partners, which provide economies of scale. This strategy also provides flexibility to fabless customers that bring in their own epitaxial wafers, as the specificities of the epitaxial layers influence the device properties.

Vertically integrated IDMs generally prefer to do their epi in-house. Transphorm is a vertically integrated GaN manufacturer pushing the envelope for larger, higher current GaN chips. “The beauty of Transphorm’s process is that it runs with silicon equipment in a silicon fab,” said Primit Parikh, president and COO of Transphorm. “For the GaN epiwafers, we have our proprietary processes on standard MOCVD equipment produced by equipment manufacturers, which constantly strive to improve their tools generation over generation to better serve their market.”

Parikh cited Transphorm’s work with Aixtron and Veeco as examples. “This gives us direct control of our GaN wafer manufacturing — a capability we see as critical to innovation, manufacturing control, quality, and ultimately supply chain control.”

Adding GaN capabilities to silicon lines is a growing trend. Consider Wavetek, UMC’s 50k/month specialty fab. First built in 2010, it transitioned to GaAs in 2014. “Leveraging our previous success with technology transition, Wavetek is converting CMOS high voltage technology to GaN power process by utilizing most of the existing CMOS tools,” said Mao Jwo, vice president of sales and marketing at Wavetek. “GaN’s wide bandgap and high-frequency performance characteristics enable us to deliver products with superior form factors and much greater efficiency to meet the increasing demand for energy-efficient devices.”

In RF, while Wavetek has good market share in communications infrastructure applications, those are PHEMT/HBT solutions employing DUV steppers. “For customers seeking better power gain and higher output power, we also offer a migration path to GaN RF technology, which uses gold BEOL interconnects,” Jwo said. “We have been working with our driving customers on GaN solutions for sub-6GHz, mmWave, and LEO satellite communications products, and we will continue to expand our relevance in this segment. In short, the Wavetek team is working closely with driving customers on both GaN power and GaN RF technology development. We believe GaN devices, with their superior energy efficiency properties, will play an important role in the transition to a greener, low-carbon future.”

Fig. 2: UMC is converting CMOS lines at its Wavetek Fab (also known as Fab 6A, located in Hsin-Chu, Taiwan) in order to expand production of high-power and RF GaN chips. Mass production is scheduled for 2023. Source: Wavetek

Suppliers step up
Equipment suppliers are taking different approaches to the GaN market, with some making greater adaptations than others. But for all of them, flexibility is key.

Drew Hanser, vice president of technology at Veeco, noted that his company uses the same equipment interchangeably for growth on silicon as well as SiC substrates for power and RF applications. “Our gas injection approach offers highly uniform concentrations by design, which results in excellent film thickness uniformity, composition uniformity, and doping uniformity,” he said. “Our single-wafer reactors also offer multi-zone heating control and an optimized thermal environment for excellent temperature uniformity for 200mm and 300mm wafers.”

Fig. 3. Veeco’s Propel 300 MOCVD System for high-volume manufacturing features single wafer reactor precision for advanced GaN-based applications, in 200mm and 300mm configurations. Source: Veeco

Screen’s approach, meanwhile, is to reconfigure existing silicon equipment for GaN processes. For photolithography tracks and cleaning tools, the big difference is that GaN-on-SiC requires careful handling due to the fragility of the SiC wafer edge, explained Lucia D’Urzo, senior manager for the European marketing department at Screen. In the scrubber tools, special brushes are used to minimize the wear from the SiC substrate. For metrology and inspection, film thickness and optical coefficients are modeled to measure the GaN, AlN, and AlGaN, while multiple lighting options and defect analysis algorithms are available to inspect transparent wafers.

“GaN device production is still dominated by 150 and 200mm wafers,” D’Urzo observed. “One of our strengths is that we have an extensive tool suite that can flexibly handle the production of various devices at these wafer sizes.”

Fig. 4: The Screen ZI-3500 is a high-speed automatic visual inspection (AVI) system for GaN and SiC wafers from 150mm to 300mm. Source: Screen

Looking ahead, she sees wafer surface preparation prior to epi growth and optimization of the MOCVD process itself, especially when dealing with larger wafer size, as one of the biggest challenges for GaN. Another is inspection. “We are still facing crystal defects with the GaN films compared with silicon, and cracks and slip lines develop from suboptimal MOCVD processes,” she added. “We have a portfolio of cleaning tools to ensure advanced surface cleaning processes, while our inspection tool, ZI-3500, can offer 100% wafer sampling at a reasonable throughput and low CoO.”

Other suppliers are taking a more specialized approach. “Through an ongoing development program, Lam Research has been establishing a suite of enabling process solutions for GaN semiconductor device fabrication,” said David Haynes, vice president of specialty technologies in Lam Research’s Customer Support Business Group. “Key to these capabilities is an atomic layer etch-based process that can provide ultra-low damage, atomic scale precision etching of GaN and related materials. The new, optimized processes can reduce the post etch sheet resistance of the as-etched GaN/AlGaN [aluminum gallium nitride] whilst the surface roughness of the etched material remains comparable to that of the incoming epitaxial layers. Such high-precision, low-damage etch capabilities are critical to the formation of p-GaN or recessed gate high electron mobility transistor (HEMT) architectures used to fabricate normally off GaN devices for power electronics applications.”

And while such a process typically would be slow, Lam has developed proprietary solutions to speed it up. This can be used in both RF and power GaN fabrication.

“Although GaN on SiC RF devices are comparatively well established and will remain very important for high power applications — for example, in telecommunications infrastructure and defense — the rapid evolution of GaN-on-Si epitaxy means that GaN-on-Si RF devices will increasingly address lower power, high volume applications for consumer products,” Haynes said. “These will evolve alongside GaN-on-Si power devices that share many of the same process challenges. Today, most GaN-on-SiC RF devices are still made on 150mm or even 100mm wafers. The opportunity for GaN-on-Si devices to be readily processed on 200mm and in the future 300mm wafers, as well as the potential to use complementary metal-oxide semiconductor (CMOS) foundry capacity and even develop integrated solutions with CMOS, will all be key drivers for this transition.”

Fig. 5: Lam’s Kiyo45 reactive ion etch (RIE) tool processes GaN and SiC materials, which cannot be wet etched. Source: Lam Research

Haynes noted there are numerous other plasma deposition and clean process steps that are critical to improving GaN device performance. Lam is working to optimize both the passivation process itself and the pre-passivation surface cleaning of the wafers. Lam also addresses the challenge of gallium contamination on the wafer backside and bevel. And, of course, there is the overarching challenge associated with the transition from 150mm to 200mm wafers, said Haynes. “That’s why our approach of developing solutions using established high-volume manufacturing tools makes so much sense. It provides the best 200mm capability while offering a future bridge to 300mm production using the same tools.”

The importance of packaging
The front end is not the only place where advances are occurring. As GaN pushes into new frontiers, new packaging solutions are required. QP Technologies (formerly Quik-Pak) is a leading provider of microelectronic packaging and assembly, wafer preparation, and substrate design and development services. “The package is an integral part of the overall performance,” said Tom Bianchi, QPT’s sales director.

As the chip performance increases, the package and connect technology demands increase, Bianchi noted. GaN is pushing the back-end material demands for better die attach and enhanced wire bond technology. “That’s why QPT is working with equipment manufacturers to enhance wirebond design to optimize GaN RF performance,” he said.

QPT offers wafer finishing (thinning, metallization and dicing), and all forms of assembly, including power custom packaging. One of the packaging challenges for GaN-on-silicon power devices is dicing, because GaN is much harder than silicon and tends to chip. The QPT solution involves dual-spindle dicing saws, which enables the use of two different dicing blades. One removes the GaN, while the other is for the silicon. QPT also has partnered with a major dicing equipment supplier to provide laser scribing and ablation when required.

Looking ahead, Bianchi sees opportunities for improvements in package customization to better handle thermal for power, lower impedance materials, package design, and processes for RF.

Vertical horizons
Historically, today’s GaN power devices descend from HEMTs first designed for the RF world. These are lateral, “always on” devices, which is necessary for RF. But for power, “always on” is a security risk. Power devices need to be “always off,” so GaN designers have developed strategies to make them stay off until they’re turned on.

In lateral devices, the current flows “horizontally” through the electrical channel between the AlGaN buffer layer and the top GaN layer. Generally speaking, to enable power devices to handle higher voltages, the distance between the source and the drain needs to be extended, and the buffer layers grown thicker.

There is a lot of work underway to push GaN voltages higher. In 2021, for example, imec and Aixtron demonstrated epitaxial growth of GaN buffer layers qualified for 1,200V applications on 200mm QST substrates, with a hard breakdown exceeding 1,800V. “The manufacturability of 1,200V-qualified buffer layers opens doors to highest voltage GaN-based power applications such as electric cars, previously only feasible with silicon-carbide (SiC)-based technology,” contends imec.

However, in lateral devices, supporting higher voltages comes at a cost. Spacing the source and drain further apart is a horizontal exercise, and that means bigger chips — which in turn means fewer chips per wafer. The jury is out as to how far lateral GaN devices will be able to go in increasing voltage cost-effectively.

The other option is to go vertical. Silicon and SiC power devices are vertically oriented, meaning that structurally the source of the device is at the top, and the current flows down (vertically) to the drain, which is on the bottom. To increase the voltage the device can handle, all that’s required is to make the device thicker, so the source is further from the drain. This provides an entry into the world of ultra-high voltage, where applications demand ranges from 3.5kV for railway traction to 10kV and beyond for smart energy grids.

There is work underway to take a similar approach with GaN device, but there are plenty of catches to making vertical GaN power devices. First, that requires an essentially perfect crystalline structure from top to bottom, so you can only increase the thickness by doing GaN epi on bulk GaN wafers — no big buffer layers on silicon wafers as with lateral GaN. Bulk GaN wafers, however, are really small, ranging from just 1 to 4 inches. That invokes a financial challenge in an industry that addresses productivity challenges by going to bigger and bigger wafers. (Like their SiC cousins, GaN boules — aka ingots — are small and slow to grow). On the plus side, vertical GaN devices are very small, so you can fit many more on a wafer.

As noted by Veliadis, to do vertical GaN, “You need large substrates, a decent cost, good quality. Then you’re going to need specific processes for vertical GaN that don’t exist in silicon, and you need to develop those processes, and you need to have tools for those processes.” All of this requires substantial investments across the industry. Silicon carbide, meanwhile, has a 10-year head start.

Vertical GaN has yet to be commercialized, although companies like NexGen and Odyssey Semi say they’re close. Research also is underway at imec. Veliadis noted, however, that because the available market for lateral GaN power devices has a sweet spot of 600V that is so immense, research funding for vertical devices is suffering.

As noted by Yole (see Figure 6) GaN power devices currently handle markets for high-volume fast chargers for phones and low-volume high-end photovoltaic inverters. These are lateral devices that also are making headway into the automotive domains of on-board chargers (converting the AC from the wall outlet to DC optimized for EV batteries), DC/DC conversion (stepping down the DC power from the 400 or 600V car batteries to the 12V or 48V needed by all the accessories), and data centers. In data centers, the push is egged on by the requirements of 80 PLUS platinum- and titanium-grade power supplies for better energy efficiency, said the Yole experts. (80 PLUS is a certification program that rates energy efficiency of computer power supplies.)

Fig. 6: Yole sees very strong growth for GaN power devices across different applications between now and the end of the decade. Source: Yole Group

Will vertical GaN devices be required to make the leap to inverters for EV/HEV and industrial markets? Those inverters convert the high-voltage DC power in the battery to the AC power needed by the motors powering automotive wheels or heavy industrial machinery. The question then is, “Will the industry put the resources into GaN to make that vertical leap, or will ultra-high voltages remain the domain of SiC and silicon?” Clearly, it is a horserace, and only time will tell.

Conclusion
Although GaN markets are tiny compared to silicon, they are strategic and very promising. IDMs and foundries are partnering with equipment manufacturers and designers to maximize energy efficiency and decrease costs. Through the end of the decade, there will be an enormous boom in GaN production for power and RF, and equipment suppliers are working with their customers to ensure optimal performance. Whether the industry extends that cooperation to the end of the decade to enable vertical GaN, or whether SiC and silicon will dominate the important high-voltage inverter niche, remains to be seen.

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