Why new designs and process flows could help overcome manufacturing challenges.
Key Takeaways:
Gallium nitride power devices have made significant inroads into low-voltage applications like chargers for consumer electronics. High-voltage applications like power generation and transportation have more demanding requirements and have, so far, been more skeptical of GaN’s potential.
Requirements for power devices can be summarized by Baliga’s figure of merit [1]:
where ε is the dielectric constant, μe is the electron mobility, and Ec is the critical field. The drift layer resistance is then given by:
where VB is the breakdown voltage. In a comprehensive review, Tetsu Kachi of Nagoya University noted that the critical electric field, Ec, in wide bandgap semiconductors like SiC and GaN is up to 10 times that of silicon. These materials offer superior breakdown characteristics with lower resistance. [2]
The performance difference between SiC and GaN, on the other hand, is less clear-cut. Silicon carbide offers superior thermal conductivity (4.9 W/cm-K versus 1.3 W/cm-K for GaN), while GaN has better carrier mobility (2,000 cm2/V-sec versus 900 cm2/V-sec for SiC), thereby giving designers more flexibility. [3]
However, the potential advantages of GaN have been slow to materialize because the material is so hard to manufacture. While silicon and silicon carbide are both available as large, freestanding wafers, GaN is typically grown on silicon substrates. A thick transition layer accommodates the lattice and thermal expansion mismatch between GaN and silicon. As a result, GaN-on-silicon substrates incorporate a lot of stress, making them fragile and prone to breakage, according to imec’s Karen Geens. [4]
Optical GaN devices have developed more quickly than power devices, in part because optical devices are smaller. Power devices need a larger area of high-quality, dislocation-free material.
Most commercial GaN power devices depend on lateral conduction. A two-dimensional electron gas (2DEG) at the interface between GaN and AlGaN allows current to move freely within it, but not in or out of the plane. Unfortunately, breakdown voltage depends on the gate-to-drain distance. High-voltage devices with lateral current flow need larger footprints. The thin 2DEG layer also poses reliability risks due to surface and interface traps.
Silicon and SiC devices use vertical designs to increase the gate-drain distance as needed. Building vertical devices in GaN is difficult because designers need either GaN-on-GaN substrates or the ability to reach the GaN device’s backside through the silicon substrate.
In recent years, Kachi said, advances in GaN growth techniques have improved the quality of GaN-on-GaN substrates. Engineered substrates can also be used as a potential starting material for thick GaN layers. Geen’s group investigated Qromis Substrate Technology (QST) wafers, in which a polycrystalline AlN core is surrounded by encapsulation layers, topped by an SiO2 bonding layer and a single-crystalline silicon growth template layer. These substrates are mechanically strong and more closely match GaN’s thermal expansion behavior. With these improvements, vertical designs — and the processes needed to build them — are starting to deliver kilovolt-level breakdown voltages in a reasonable device footprint.
Doping GaN structures
Doping is one of the first process challenges for complex GaN structures. It’s relatively easy to change the composition of a blanket GaN layer by adding dopants to the deposition chemistry. But creating selectively doped regions, such as p-doped wells in an n-doped layer, is harder. It requires tools like ion implantation.
Somewhat unintuitively, n-type doping for GaN power devices is difficult in part because the desired dopant concentration is so low, one or two orders of magnitude lower than needed for GaN optical devices. When metal-organic precursors are used to grow the GaN layer, some amount of carbon contamination is inevitable. As the intended dopant (usually silicon or germanium) concentration decreases, unintentional carbon doping offsets it and degrades the ultimate carrier mobility, increasing the device resistance.
Carbon contamination poses similar challenges for p-type devices using magnesium. In low-dose p-type doping, Kachi said, carbon can form both donors and acceptors on nitrogen sites, as well as donors on gallium sites. At high doses, magnesium precipitates can form. Both high-dose and low-dose concerns are relevant as the intended magnesium doping concentrations range from 1017/cm3 to 1020/cm3, depending on the device layer.
Once dopant atoms are in place, the next issue is dopant activation. Ryo Tanaka of Fuji Electric explained that the GaN surface decomposes above 800°C, requiring an AlN protective layer.[5] But even with the protective layer, the baseline process achieved only 20% p-GaN activation after annealing at 1,300°C for 5 minutes. In n-GaN, Kachi reported that an additional nitrogen implantation step can be used to occupy nitrogen vacancies, helping to push silicon or germanium into gallium lattice sites. In p-GaN, following magnesium with nitrogen implantation helps pin magnesium ions in place, both reducing diffusion and improving activation.
Vertical MOSFET designs
Improvements in selective doping greatly expand the library of potential GaN device structures. As in silicon, ion implantation allows manufacturers to achieve precise dopant profiles. With this flexibility available, the industry has not yet converged on a single design. One leading candidate, the trench gate MOSFET (Fig. 1e, Fig. 2) is attractive because it offers a simple, relatively easy to fabricate structure.
Fig. 1: Vertical GaN devices reported to date. Image courtesy of reference [2]
Fig. 2: Vertical GaN trench gate MOSFET design. Image courtesy of reference [2]
Trench formation is a critical process step for this design. Flat, undamaged sidewalls give a clean current path, while rounded corners avoid current crowding. Kachi reported their best results with Cl2 and SiCl4 etch gases. The Cl2 promotes etching by reacting with GaN to form volatile species like GaCl3 and NCl3. Meanwhile, SiCl4 forms silicon nitrides and oxides, helping to passivate trench sidewalls.
Like other aspects of vertical GaN device integration, the industry has not yet identified the best gate dielectric. Several groups have used an Al2O3/SiO2 bilayer, reporting that the bilayer is more robust against breakdown failures than aluminum oxide alone. Increasing the SiO2 thickness improves the device failure voltage independent of magnesium concentration or trench sidewall cleaning. M. Ruzzarin of the University of Padova noted that this is an expected result: a thicker dielectric of any material will reduce the effect of surface traps. [6]
More recently, Kachi used an AlSiO dielectric, deposited by plasma-enhanced ALD of Al2O3 and SiO2. They achieved their best results at about 21% silicon, with SiO2 interlayers added to prevent crystallization at the GaN surface. Still, the mobility of these devices was lower than expected.
Indeed, the good news from recent results is that the individual process modules needed for fully integrated vertical GaN power devices are in place, and the industry has identified designs that can deliver competitive high-voltage behavior. Still, almost all device elements need improvement, from better magnesium implantation and activation to better models of the integrated devices. GaN may be the future of high-voltage power management, but the future isn’t here just yet.
References
Related Articles
GaN Power Devices Power Up
New research points to safer devices with less loss at low voltages, but problems remain for high-voltage industrial applications.
Electrifying Everything: Power Moves Toward ICs
Wide bandgap materials and advanced packaging are revolutionizing power, but thermal and integration challenges persist.
Improving GaN Device Architectures
Novel combinations show promise for different applications.
 |
 |
 |
 |
 |
 |
 |  |
 |
 |
 |
Leave a Reply