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Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna)

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Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.”

This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through physical design and manufacturable layouts.

Find the technical paper here. June 2026.

Zelioli, Enrico, Philippe Sauter, Thomas Benz, Hannah Pochert, Luisa Wüthrich, Beat Muheim, Frank K. Gürkaynak, and Luca Benini. “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” arXiv preprint arXiv:2606.25673 (2026).



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