PCB And IC Technologies Meet In The Middle

Surface-mount technology (SMT) is evolving far beyond its roots as a way of assembling packaged chips onto printed circuit boards without through-holes. It is now moving inside packages that will themselves be mounted on PCBs.

But SMT for advanced packages isn’t the same as the SMT we’ve been used to.

“Many systems include multiple ASICs, a lot of memory, and that’s all integrated into a very small footprint,” said Kenneth Larsen, product marketing director at Synopsys. “It’s almost like you take the entire PCB and squeeze it into a very small form factor.”

Advanced packages use interposers or other substrates for mounting dies. Those interposers are like mini-PCBs, albeit made from differing materials. But the dimensions for metalizing redistribution layers (RDLs) are typically much more aggressive than those used on a PCB, even though they’re large by semiconductor standards. As a result, ideas must be brought to bear from both the PCB side and the semiconductor side to ensure good manufacturability.

“You have companies that are more PCB-centric and approach it from the packaging PCB side, but you have other companies that are more chip-centric, and they view it from the chip side,” said Marc Swinnen, director of product marketing for semiconductors at Ansys. “However, the two worlds are being pulled closer together, and a lot of companies are not set up for this.”

This leads to something of a dilemma for chipmakers. “Are you going to use modern tooling from semiconductor fab guys?” asked Steve Ledford, general manager of device interface at Teradyne. “Or are you going to use modern tooling from PCB and SMT manufacturing guys?”

While advanced packaging isn’t new, it is still early in its production life, and applications tend to be limited. As costs come down and more applications use the tighter integration that such packaging provides, more companies will be able to take advantage of it. So it can be helpful to back out to a high level and get some perspective between the original SMT and the newer variants.

“Between the stacking phenomenon and SMT, advanced packaging is halfway between conventional front end and conventional back end,” said Subodh Kulkarni, president and CEO of CyberOptics. “And that’s where all the innovation is happening right now. Crack open any modern device, and the advanced packages that are strung together look very different from what the boards looked like 10 years ago.”

Package interposers do the same job as a PCB, facilitating connections between the components mounted onto them. In addition, they provide the wiring that eventually will connect to the bumps and the PCB. And many of the notions necessary for PCB manufacturing play out on an interposer, but in miniature. Entire systems consisting of computing, memory, and even analog I/O can be assembled and then encased as a package to be installed on the PCB.

While this may sound like a simple scaling down of a PCB for installation onto a meta-PCB, it’s not quite that easy. Any such assembly process requires inspection and test for quality assurance, but the tools used for inspecting and testing PCBs don’t necessarily scale to the package level. It’s all SMT, but different equipment is required based on the different materials in use and the dimensions of interposer features.

Materials used for substrates
High-volume commercial PCBs are typically made from FR-4, a fiberglass/epoxy combination that has been a PCB favorite for decades. While it can be shrunk for small mezzanine cards and other smallish boards, minimum line pitch is measured in mils, not microns. Minimum pitch is typically in the range of 5 or 6 mils (getting somewhat lower for specialty applications), which translates to something over 100 microns.

Fig. 1: A typical PCB made of FR-4. Source: Raimond Spekking / CC BY-SA 4.0 (via Wikimedia Commons)

Converting to microns is useful, because advanced package substrates can support dimensions measured in microns. So right away there’s an immediate shrink of an order of magnitude. Exactly where they fall in the micron realm depends on the substrate material as well.

There appear to be two words used when describing the “mini-PCB”-looking thing inside a package. Sometimes they’re simply called substrates, while other times they’re called interposers. There doesn’t appear to be a formal definition distinguishing substrates from interposers, but common usage in this context seems to apply substrate for organic materials and interposer for inorganic materials. (Technically, an interposer is a substrate.)

PCBs may have many layers for complex routing and shielding, but substrates and interposers tend to have a very few layers — maybe only one, often referred to as a redistribution layer (RDL). The organic substrates are normally found in so-called panel applications. Those are similar to semiconductors in that multiple units are fabricated on a single large piece before being cut into individual units. The big difference is that because of the way they’re manufactured, the panels can be rectangular, meaning nothing is wasted when cutting them up. This technology is largely derived from the display industry.

“Why square dies work on a round wafer isn’t so much because wafers are the ideal thing to fit square things,” said Ledford. “It’s because that’s the way silicon ingots are pulled.” So the rectangular interposers end up being singulated from the circular wafer, which means that there will be waste around the edges.

Fig. 2: Wafers force the fitting of rectangles onto a circle, resulting in some waste. Panels start with a rectangle, allowing better use of the space at the expense of dimensions. Source: ASE

Glass is another promising candidate in the early stages of development. “Glass can be both round or square,” noted Ledford. Glass substrates are also often referred to as interposers.

So that makes for three basic variants of SMT substrates: PCBs, panels, and interposers. They have significant cost and dimensional differences.

Dimensions and manufacturing
“Everything converges to semiconductor-like dimensions,” said Ledford. “It’s just a matter of time. When I came out of school, mainstream semiconductors were 1 micron line and space. If you look at where advanced packaging is now, it’s getting really close to 1 micron line and space. It just took 30 years for it to reach that point.”

There are two critical aspects to the dimensions needed on any of these materials. First, there’s the minimum pitch. But just as important can be the control of those dimensions.

“Test and measurement are all about 50-Ω controlled impedances,” said Ledford. “That means that the manufacturer of that line needs to have dimensional control of a quarter micron. Well, if I go talk to any of my PCB shops, they don’t have anywhere close to that level of dimensional control.”

The primary reason for that is the chemistry: PCBs are made using wet chemistry, and that limits both the dimensions and their tolerances. “Wet chemistry processes, which dominate PCB and [traditional] SMT, don’t have the dimensional control that you need,” said Ledford. “What kind of process does give you quarter micron line and space control? Dry processes — sputtering, dry etch, and things like that, which come primarily from the semiconductor domain.”

While multiple PCBs can be processed at the same time in some kind of bath, panels and wafers must be handled individually in their reaction chambers. This is one of the major costs associated with smaller form factors.

“The main reason semiconductor manufacturers are moving to panel-level packaging is due to large dies in a system-in-package (SiP),” said Woo Young Han, product marketing manager at Onto Innovation. “Multiple chips, including CPU, GPU, DSP, and memory, are packaged into a single base, and the result is much larger than traditional die sizes experienced in the semiconductor industry. SiP die sizes can be as large as 100 mm, so a 600-mm rectangular panel is a much better choice than a 300-mm circular wafer for manufacturing large SiP dies.”

Silicon interposers are limited by the wafer size, so that makes them more useful for integrating a processor with a more limited amount of memory. Chiplets are also candidates for integration into these smaller packages.

Using a panel provides for more large dies, but it comes at the expense of how close you can put lines or chips together. “Panel-level packaging may have larger GPUs or CPUs, but not necessarily the close proximity of a chiplet,” said Robert Cid, product line manager, white light interferometers at Bruker.

That said, while one might expect panels to be a middle ground on the way to wafer-level integration, it may actually go the other way. “I see panel-level packaging becoming more of an enabling solution for those companies that want to do more integration,” noted Cid. “If wafer-level packaging starts to migrate over to larger substrates, there could be potential for driving costs in packaging down even further.”

The major functional difference between PCBs and any of these other options is the number of interconnections that can be managed. “You’re not talking about just a few 40-µm I/O pads,” said Ledford. “You’re talking about thousands of 40-µm I/O pads.”

Others agree. “You can have thousands of these micro-bumps and very dense traces in between,” noted Randy Fish, director of marketing for silicon lifecycle management in Synopsys’ Digital Design Group. “And being able to have redundant interconnect is a necessary part of that.”

Inspecting the lines
One of the major process differences between PCB and advanced packaging lies in inspection — especially the ability to do rework where flaws are found.

“In a typical PCB inspection flow, the inspection module performs inspection on PCBs, and then the PCBs are transferred over to the review station for operator review — and then sent over to a repair station to repair the defects found,” explained Han. “In the semiconductor wafer-inspection world, repairing individual defects is unthinkable in both the front-end and back-end semiconductor processes.”

Humans still figure in the PCB inspection world. “Because of the historical nature of the PCB industry, they still see a lot of manual inspection stations for operators looking through microscopes,” said Ledford.

CyberOptics’s Kulkarni described his surprise when looking at the end of a DIMM manufacturing line. “There were 20 people standing around that area with white lights next to them,” he said. “And they were literally picking up every single memory board from the conveyor and inspecting both sides visually before putting them in plastic bags.”

The DIMMs underwent a final I/O test, but they were inserted warm. A half a minute later, when removed, they had cooled significantly, and they didn’t pull out so easily — sometimes disturbing the memories on the board. “Even though the I/O check looked fine, by the time the customer got it, it wasn’t good,” explained Kulkarni.

Adding an automated final inspection step now allows intervention with any boards that need rework without the need for human inspection.

Sockets intended for holding large CPUs or other such expensive chips are another example. Sockets are used so that if there’s a board problem, the high-value chips can be easily removed and moved to a new board rather than being discarded with the board.

“In a three-by-three-inch square, you have 10,000 pins,” said Kulkarni. “And these are literally hairy little copper things that are coming out and bending over because there has to be some kind of spring.”

That makes them very hard for humans to inspect. A visual tool can again automate that process, improving results and throughput. So there has been movement toward higher levels of automation with PCB inspection.

But moving inside an advanced package, the dimensions and the number of signals make it completely impractical to inspect by hand. Automation is required. How those tools work differs, however, between PCBs and panel- and wafer-level assemblies.

“Large die size is common in the PCB world, and traditional PCB inspection tools use a method based on CAD design rules,” said Han. “In the semiconductor world, inspection tools are designed to find much smaller defects on highly repeating die patterns, so inspection tools in the semiconductor world use a golden-die or neighbor-die comparison method. SiP dies have a lot more die-to-die variation compared to semiconductor wafers, and the CAD design-rule method works better than the golden/neighbor-die comparison method. This is an advantage for traditional PCB inspection tools. SiP dies also have much smaller design rules compared to traditional PCB die designs — as small as 2-µm trace width — and require sub-micron defect detection. However, PCBs use trace widths larger than 10 µm, and the traditional PCB inspection tools do not have the optical resolution to perform sub-micron defect detection. This is an advantage for semiconductor wafer inspection tools.”

Panel dimensions are somewhat larger than interposer dimensions, but it’s still likely that semiconductor equipment would be used — with relaxed numbers. “If you have a 600 x 600-mm size, you want to make sure that the features across the whole panel are within spec,” said Cid. “And that could be a challenge. We’ve seen customers asking for ways of expediting metrology to survey a larger area in order to assess the quality of this panel before it goes to production.”

Still, it would be a mistake to assume that panels and interposers have similar inspection. “We’re seeing the requirements for both wafer level and panel level packaging be very different,” said Cid. “We have tools that are specifically designed for panel-level packaging, with different requirements from the tools we design for wafer-level packaging.”

That said, it’s partly a situation where panels lag interposers. “The roadmap discussions we’ve heard suggest that panel-level processing requirements are going to become more complex, requiring some of the rigorous metrology that you have for wafer level packaging a few years out,” said Cid.

So while automation and AI are moving into the PCB-inspection world, those technologies are essential for advanced packages.

Testing boards, substrates, and interposers
Testing brings together completely different philosophies. Traditionally, PCBs have been tested using bed-of-nails testers that can quickly verify all of the connections on the board. But each board needs a custom fixture, adding friction to the test-development process.

JTAG has made that somewhat easier, providing a way to chain together all of the components on the board and test their connectivity. This was the original goal of JTAG, and it was only later that the internal chip-testing capabilities were expanded. So in principle, it’s possible to test both connections and functions using a single JTAG port.

ICs, by contrast, use internal self-tests as well as externally delivered vectors that may use dedicated test pins or other pins that double as test access pins in a test mode. A critical difference from PCB test is that, with ICs, functionality is tested. With PCBs, it’s primarily about testing connections. The ICs on the PCB are assumed to work based on the individual testing they’ve gotten as part of their manufacturing flow.

Advanced packages lie somewhere in the middle, and exactly what gets tested when will have a huge impact on cost. That’s because one is working with dies that have been tested and then singulated, placing them on the substrate or interposer, which itself has to be tested to ensure that the connections are working properly.

But have those dies been damaged in the singulation process? Does the substrate/interposer assembly need to be tested on its own, both for connectivity and functionality to ensure that everything survived the assembly process? Should the interposer be tested before the chips are applied and then again after? And if the whole thing is going to be tested, should that be before or after encapsulation — or both?

Part of the challenge is the number of internal connections that never make it to an external connection. “A lot of these internal dies aren’t made to talk to the real world,” noted Fish. “All the connections are die-to-die.”

There are no solid answers to these questions. It will vary by application and the accompanying economics — not to mention the risk of failure. More testing will be required for safety-critical assemblies than for those whose failure consequences would be limited to annoyance or loss of goodwill for the manufacturer.

“Given the option, there are going to be situations where people do want to be able to test dies within a complex package,” said Fish. “But on a lower- or mid-priced product, I don’t think you can afford to test every die again.”

There’s also an important practical impact if the dies themselves will be tested. “If you’re buying known-good dies, is that supplier going to give you their test sequence so you can run it yourself?” asked Fish.

As to the actual testing, even though the assemblies may look like mini-PCBs, a bed-of-nails approach is completely impractical due to the dimensions. The pogo pins used in such fixtures are far too large. In addition, custom fixtures per chip add an unreasonable burden and cost to the process.

JTAG can be used here, as well, although that comes with limited signal speeds. USB and PCIe are also options being leveraged for dedicated test access ports, and that can speed the testing of both individual dies and advanced-package assemblies. In fact, it can be used for PCBs as well.

“We’re moving toward high-speed dedicated I/O for test,” said Fish. “You insert our IP into your chip that connects to those I/Os on the controller side, and then connects to the test infrastructure on the die.”

Conclusion
All in all, surface-mount devices inside an advanced package must be manufactured, inspected, and tested using techniques that mostly come from the semiconductor world. While many of the ideas may have originated with PCBs, it’s often just not practical to scale PCB approaches down enough.

Because packaging is a natural part of the semiconductor manufacturing process, it’s not surprising that the advanced packages carry much of this semiconductor legacy. But the fundamental principles of attaching components to the surface of a substrate has its roots back in the PCB world. It just looks very different when shrunk down to near-semiconductor dimensions