tag: 2.5D

Reliability And Traceability In Advanced Packages
By Ed Sperling - 24 Dec, 2025 - Comments: 0

The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Thermal Modeling in Emerging Heterogeneous 2.5D/3D Systems (EPFL, Universidad Complutense de Madrid)
By Technical Paper Link - 22 Dec, 2025 - Comments: 0

A new technical paper titled "3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systems" was published by researchers at EPFL and Universidad Complutense de Madrid. Abstract "The increasing power densities and intricate heat dissipation paths in advanced 2.5D/3D chiplet systems necessitate thermal modeling frameworks that deliver detailed thermal maps w... » read more

What’s Next for 2.5D Packaging?
By Bryon Moyer - 18 Dec, 2025 - Comments: 0

Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they're built and assembled. Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges. Interposers are effectively platforms on which mu... » read more

DFT Shifts Further Left
By Ed Sperling - 08 Dec, 2025 - Comments: 0

Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

New Approaches To Limit Cyberattacks On Hardware
By Ann Mutschler - 09 Oct, 2025 - Comments: 0

The number and value of cyberattacks on semiconductors is rising, but new approaches to designing and packaging chips could put a significant dent in those figures. Semiconductor-related cybersecurity attacks have multiplied more than six times since 2022, according to a report by cyber intelligence firm CloudSEK. These attacks have cost the semiconductor industry an estimated $1.05 billion ... » read more

How To Cool 3D-ICs
By Ed Sperling - 01 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what's missing from the tool chain today, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysigh... » read more

First Forays Into True 3D-IC Designs
By Ed Sperling - 25 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

Mitigating Warpage In Multi-Chiplet Systems
By Laura Peters - 22 Sep, 2025 - Comments: 0

Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Chiplet Interfaces Embrace Failures
By Anne Meixner - 12 Aug, 2025 - Comments: 0

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy