Nanofabrication Protocol That Allows Patterning Metallic Electrodes on 2D Materials Reliably (KAUST, National University of Singapore)


A new technical paper titled "High-yield photolithography protocol to pattern metallic electrodes on 2D materials without adhesive metallic layers" was published by researchers at KAUST and National University of Singapore. Abstract "When using two-dimensional (2D) materials to build electronic devices, adjacent metallic films need to be deposited to form electrodes. However, weak adhesion ... » read more

GPU Acceleration Of Rigorous Lithography Simulations


Producing modern semiconductor devices is an immensely challenging process. Successful execution entails advanced process nodes, novel device architectures, new materials, and many fabrication steps. One especially challenging area is lithography, in which light is sent through a photomask, passes through a projection system of lenses and mirrors, and strikes the substrate to create the device ... » read more

40th EMLC Honors Three Decades Of Vision From Dr. Uwe Behringer


The European Mask Lithography Conference (EMLC), an annual event that brings together researchers from around the world to present the latest findings on photomask and lithography technology, returned to Dresden from June 16 to June 18, 2025, and took place for the 40th time – marking a memorable anniversary combined with a premiere. For over 30 years, Dr. Uwe Behringer shaped the conference ... » read more

Are Larger Reticle Sizes On The Horizon?


Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

Photomask Changes And Challenges At Mature And Advanced Nodes


Experts at the Table: Semiconductor Engineering sat down to discuss the current state and future direction of mask-making, with Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows are excerpts of that conversation.... » read more

Determinants Of Bond Wave Speed In Wafer Bonding (Yokohama, TEL)


A recent technical paper titled "Factors determining bond wave speed in wafer bonding" was published by researcher at Yokohama National University, Tokyo Electron Kyushu Limited and ANVOS Analytics. Abstract "Wafer-level direct bonding has become a critical process for advanced 3D architectures in logic, memory, and CMOS image sensors. The minimization of the wafer distortion caused by wafe... » read more

Quantifying The PFAS Impact In ICs Manufacturing (Harvard University)


A new technical paper titled "Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems" was published by researchers at Harvard University and Mohamed Bin Zayed University of AI (MBZUAI). "The electronics and semiconductor industry is a prominent consumer of per- and poly-fluoroalkyl substances (PFAS), also known a... » read more

Scalable Approach For Fabricating Sub-10nm Nanogaps


A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Reflecting On The SPIE Advanced Lithography + Patterning Symposium 2025


The mood at this year’s SPIE Advanced Lithography + Patterning Symposium was decidedly upbeat. The outlook for business is good, due in large measure to expectations of high demand for chips, driven by artificial intelligence (AI). To realize the potential of AI, increases in chip performance and efficiency are needed, which, in turn, requires advanced patterning. In the Symposium’s technic... » read more

EUV’s Future Looks Even Brighter


The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry's ability to meet demand. The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on ... » read more

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