Algorithm–HW Co-Design Framework for Accelerating Attention in Large-Context Scenarios (Cornell)


A new technical paper titled "LongSight: Compute-Enabled Memory to Accelerate Large-Context LLMs via Sparse Attention" was published by researchers at Cornell University. Abstract "Large input context windows in transformer-based LLMs help minimize hallucinations and improve output accuracy and personalization. However, as the context window grows, the attention phase increasingly dominates... » read more

Chip Industry Week in Review


SK hynix is ramping HBM manufacturing capacity to meet explosive demand for AI data centers. The company will launch 16-stack HBM4 next year, and up to 12-stack HBM4E. HBM5 and HBM5E will be introduced between 2029 and 2031, reports Business Korea. China will not have access to NVIDIA’s most advanced chips, President Trump told 60 Minutes. The Dutch economy minister said Nexperia's chip... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Chip Industry Technical Paper Roundup: Oct. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=480 /] Find more semiconductor research papers here » read more

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)


A new technical paper titled "Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage" was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract "Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices... » read more

Chip Industry Technical Paper Roundup: Sept 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=478 /] Find more semiconductor research papers here. » read more

Performance And Energy Characterization Of A Commercial Compute-in-SRAM Device (Cornell, USC, MIT, GSI)


A new technical paper titled "Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device" was published by researchers at Cornell University, USC, MIT and GSI Technology Inc. Abstract "Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evalu... » read more

Research Bits: Sept. 2


Microwave neural network Researchers from Cornell University designed an on-chip microwave neural network that can perform real-time frequency domain computation for tasks like radio signal decoding, radar target tracking, and digital data processing. By using interconnected modes produced in tunable waveguides, the device can handle data streams in the tens of gigahertz while consuming less t... » read more

Chip Industry Technical Paper Roundup: August 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=467 /] Find more semiconductor research papers here. » read more

Chip Industry Week In Review


The EU’s tariffs on semiconductors will not exceed 15%, according to Trump’s latest trade deal. In addition, the EU committed to purchasing at least $40 billion worth of U.S. AI chips as well as other investments. [FAQ is here.] Lifelines for Intel: Intel inked a deal to sell the U.S. government a 10% non-voting equity stake in its business, worth $8.9 billion. The stake will be fun... » read more

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