Chip Industry Technical Paper Roundup: Sept 23

Compute-in-SRAM device workloads; resilient memory design; KAN acceleration; long-context agentic LLM inference; HW design divergence for HPC workloads; analog in-memory computing, LLMs; undervolting-based static side-channel attacks; RISC-V.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference University of Cambridge, Imperial College London, University of Edinburgh
Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions Tampere University
Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology – Hellas, University of Houston Clear Lake
Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device Cornell University, USC, MIT, GSI Technology Inc.
SCREME: A Scalable Framework for Resilient Memory Design University of Central Florida, University of Texas at San Antonio, University of Rochester
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems Georgia Institute of Technology, National Tsing Hua University, TSMC
Analog in-memory computing attention mechanism for fast and energy-efficient large language models Forschungszentrum Jülich, RWTH Aachen
Chypnosis: Stealthy Secret Extraction using Undervolting-based Static Side-channel Attacks Worcester Polytechnic Institute, Ruhr University Bochum

Find more semiconductor research papers here.



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