tag: Fraunhofer IZM

Fan-Out Panel-Level Packaging Hurdles
By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Week In Review: Design, Low Power
By Jesse Allen - 03 Mar, 2023 - Comments: 0

Apple plans to spend an additional €1 billion (~$1.1B) over the next six years to expand its Munich, Germany-based Silicon Design Centre, including the construction of a new research facility. "The expansion of our European Silicon Design Centre will enable an even closer collaboration between our more than 2,000 engineers in Bavaria working on breakthrough innovations, including custom sil... » read more

Fan-Out Packaging Gets Competitive
By Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Technical Paper Round-up: June 14
By Linda Christensen - 14 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Cu/SiO₂ Hybrid Bond Interconnects
By Technical Paper Link - 10 Jun, 2022 - Comments: 0

Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

Week in Review: Manufacturing, Test
By Linda Christensen - 10 Jun, 2022 - Comments: 0

Breaking the Logjam The U.S. government’s delay in funding strategic chip capacity is threatening supply chains that are critical to national security. In fact, classified meetings are being held this week on the subject. Meanwhile, recognizing that time is of the essence, a group of billionaires has backed the “America’s Frontier Fund,” a non-profit group that aims to spur U.S. chipma... » read more

Next Steps For Panel-Level Packaging
By Mark LaPedus - 20 Dec, 2021 - Comments: 1

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Manufacturing Bits: Aug. 24
By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Manufacturing Bits: June 16
By Mark LaPedus - 16 Jun, 2020 - Comments: 0

GaN power modules Gallium-nitride (GaN) devices are emerging in several markets, such as power semiconductors and RF. GaN, a binary III-V compound, is a wide-bandgap technology, meaning it is faster and more efficient than silicon-based devices. GaN has 10 times the breakdown field strength with double the electron mobility than silicon. Generally, some GaN vendors don’t use a traditio... » read more

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