tag: Lam Research

Foundries Prepare For Battle At 22nm
By Mark LaPedus - 19 Nov, 2018 - Comments: 0

After introducing new 22nm processes over the last year or two, foundries are gearing up the technology for production—and preparing for a showdown. GlobalFoundries, Intel, TSMC and UMC are developing and/or expanding their efforts at 22nm amid signs this node could generate substantial business for applications like automotive, IoT and wireless. But foundry customers face some tough choic... » read more

Some Chipmakers Sidestep Scaling, Others Hedge
By Ed Sperling - 15 Nov, 2018 - Comments: 0

The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

EUV Mask Blank Battle Brewing
By Mark LaPedus - 15 Nov, 2018 - Comments: 2

Amid the ramp of extreme ultraviolet (EUV) lithography in the market, suppliers of EUV mask blanks are expanding their production. And a new player—Applied Materials—is looking to enter the market. AGC and Hoya, the two main suppliers of EUV mask blanks, are adding capacity for these critical components that are used for EUV photomasks. A mask blank serves as the substrate for a photomas... » read more

Blog Review: Oct. 31
By Jesse Allen - 31 Oct, 2018 - Comments: 0

Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

3D NAND: Challenges Beyond 96-Layer Memory Arrays
By Steve Shih-Wei Wang - 24 Oct, 2018 - Comments: 0

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working ... » read more

Carmakers To Chipmakers: Where’s The Data?
By SE Staff - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Blog Review: Oct. 24
By Jesse Allen - 24 Oct, 2018 - Comments: 0

Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Oct, 2018 - Comments: 0

Chipmakers Amid ongoing delays with its 10nm process, Intel has reorganized its manufacturing unit, according to a report from The Oregonian/OregonLive. Sohail Ahmed, who has jointly led the unit since 2016, will retire next month, according to the report. The industry is racing to put extreme ultraviolet (EUV) lithography into production. TSMC recently taped-out its first 7nm chip using E... » read more

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

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