tag: Lam Research

The Week In Review: Manufacturing
By Mark LaPedus - 24 Feb, 2017 - Comments: 0

Chipmakers Recently, Intel announced plans to invest more than $7 billion to complete its previously-announced fab in Chandler, Ariz. Targeted for 7nm processes, Fab 42 will be completed in 3 to 4 years. As reported, the fab announcement was made by U.S. President Donald Trump and Intel CEO Brian Krzanich at the White House. There is more to the story. Typically, Intel has two fabs for a gi... » read more

Optimizing DRAM Development Using Directed Self-Assembly (DSA)
By Coventor - 24 Feb, 2017 - Comments: 0

Directed Self-Assembly (DSA) is an emerging technology that has the ability to substantially improve lithographic manufacturing of semiconductor devices. In DSA, copolymer materials self-assemble to form nanoscale resolution patterns on the semiconductor substrate. DSA technologies hold the promise to substantially improve the resolution of existing lithographic processes (such as self-aligned ... » read more

MEMS: A Tale Of Two Tough Markets
By Ed Sperling - 22 Feb, 2017 - Comments: 0

The MEMS market is growing rapidly, profits not so much. In most market segments, this would be a signal that more automation and standardization are required. But in the microelectromechanical systems world, fixes aren't so simple. And even where something can be automated, that automation doesn't work all the time. In fact, while MEMS devices are extremely difficult to design, build and ma... » read more

Fractilia: Pattern Roughness Metrology
By Mark LaPedus - 21 Feb, 2017 - Comments: 1

A new startup has emerged and unveiled a technology that addresses one of the bigger but less understood problems in advanced lithography--pattern roughness. The startup, called Fractilia, is a software-based metrology tool that analyzes the CD-SEM images of pattern roughness on a wafer. Fractilia, a self-funded startup, is led by Chris Mack and Ed Charrier. Mack, known as the gentleman sc... » read more

Semiconductor Process Development: Finding A Faster Way To Profitability
By Katherine Gambino - 20 Feb, 2017 - Comments: 0

Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort,... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 17 Feb, 2017 - Comments: 0

Chipmakers Toshiba’s problems have gone from bad to worse. “Toshiba postponed its earnings call by up to one month, and the chairman resigned. The provisional results show large losses in its nuclear power business, while the NAND operations remain very profitable,” said Weston Twigg, an analyst with Pacific Crest Securities, in a research note. “The next few months appear very uncerta... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2017 - Comments: 0

Synopsys' Anand Thiruvengadam investigates the challenges and tradeoffs that come with different abstraction models and use models in mixed-signal verification. Cadence's Paul McLellan highlights 16 big questions facing autonomous cars, from a presentation by Andreessen-Horowitz's Frank Chen. Mentor's Colin Walls says that when it comes to free stuff, keep an eye out for the real cost. ... » read more

BEOL Issues At 10nm And 7nm
By Ed Sperling - 31 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy