tag: Lam Research

Managing Parasitics For Transistor Performance
By Katherine Derbyshire - 30 Jan, 2017 - Comments: 3

The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

New Techniques To Analyze And Reduce Etch Variation
By Coventor - 25 Jan, 2017 - Comments: 1

Time division multiplex (TDM) plasma etch processes (commonly referred to as Deep Reactive ION Etching [“DRIE”]) use alternating deposition and etch steps cyclically to produce high aspect ratio structures on a silicon substrate. These etch processes have been widely applied in the manufacturing of silicon MEMS devices, and more recently in creating through silicon vias in 3D silicon struct... » read more

New Embedded Memories Ahead
By Mark LaPedus - 25 Jan, 2017 - Comments: 0

The embedded memory market is beginning to heat up, fueled by a new wave of microcontrollers (MCUs) and related chips that will likely require new and more capable nonvolatile memory types. The industry is moving on several different fronts in the embedded memory landscape. On one front, traditional solutions are advancing. On another front, several vendors are positioning the next-generatio... » read more

Integrating Process Models With TCAD Simulation…
By Jacky Huang - 23 Jan, 2017 - Comments: 2

Novel semiconductor technologies are creating complex process flows, which are needed to support the manufacturing of advanced 3D semiconductor structures. It can be helpful to model process flows, and their effect on a novel device, prior to physical fabrication. Process modeling is a technique that can predict the 3D structure of a device using an understanding of unit process steps. Durin... » read more

Transferring Skills Getting Harder
By Ed Sperling - 19 Jan, 2017 - Comments: 0

Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

China Unveils Memory Plans
By Mark LaPedus - 19 Jan, 2017 - Comments: 2

Backed by billions of dollars in government funding, China in 2014 launched a major initiative to advance its domestic semiconductor, IC-packaging and other electronic sectors. So far, though, the results are mixed. China is making progress in IC-packaging, but the nation’s efforts to advance its domestic logic and memory sectors are still a work in progress. In fact, China has yet to achi... » read more

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2017 - Comments: 0

Mentor's Michael White warns that while skipping a node can be appealing, be prepared for the increase in computation requirements. Synopsys' Hezi Saar checks out the benefits of moving to the MIPI I3C standardized sensor interface. Cadence's Paul McLellan highlights a talk by Eric Grosse on approaches to security and the RISC-V architecture. Applied's Mike Chudzik explains the problem... » read more

Blog Review: Jan. 11
By Jesse Allen - 11 Jan, 2017 - Comments: 0

Mentor's Ron Press examines why test hasn't become a bottleneck in creating ever more advanced semiconductors. Synopsys' Graham Etchells warns that while finFET technologies have been successful, challenges persist. Cadence's Paul McLellan shares a behind-the-scenes look at developing the Palladium Z1 emulator. The White House's Craig Mundie and Paul Otellini highlight a PCAST report o... » read more

Smart Manufacturing Gains Momentum
By Ed Sperling - 05 Jan, 2017 - Comments: 0

Smart manufacturing is gaining traction as a way of addressing increased market fragmentation while still leveraging economies of scale. The goal is to add a level of flexibility into manufacturing processes that until recently was considered impossible. Although the approach makes sense in theory, real-world implementation is proving far from consistent. Sometimes referred to as Industr... » read more

BEOL Issues At 10nm And 7nm (part 2)
By Ed Sperling - 04 Jan, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy