tag: RISC-V

Beyond The RISC-V ISA
By Gajinder Panesar - 20 Dec, 2018 - Comments: 1

For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

More Than A Core
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Gajinder Pandesar, CTO of UltraSoC, talks with Semiconductor Engineering about why heterogeneous design is changing the starting point for chip design, and why integration is now the real challenge rather than the processor core. https://youtu.be/y0rzopp5HDI » read more

Open-Source RISC-V Hardware And Security
By Ed Sperling - 12 Dec, 2018 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. What follows are excerpts of that conversation. (L-R) Joseph Kiniry, Helena Handschuh and Richard Newell. SE: Is open-source hardware more secure, or does it just open up vulnera... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

Looking Beyond The CPU
By Brian Bailey - 29 Nov, 2018 - Comments: 0

CPUs no longer deliver the same kind of of performance improvements as in the past, raising questions across the industry about what comes next. The growth in processing power delivered by a single CPU core began stalling out at the beginning of the decade, when power-related issues such as heat and noise forced processor companies to add more cores rather than pushing up the clock frequency... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Nov, 2018 - Comments: 0

M&A SMIT Holdings acquired S2C, a provider of FPGA prototyping hardware and software as well as interfaces and accessories, for $19 million, plus up to US$2 million in milestone based payments to the key management team. S2C was founded in 2003. SMIT, based in Hong Kong, makes pay TV broadcasting access and mobile point-of-sale payment systems for the Chinese market. Tools & IP Syn... » read more

The Week In Review: Design
By Jesse Allen - 02 Nov, 2018 - Comments: 0

M&A GlobalFoundries formed Avera Semiconductor, a wholly-owned subsidiary focused on custom ASIC designs. While Avera will use its relationship with GF for 14/12nm and more mature technologies, it has a foundry partnership lined up for 7nm. The new company's IP portfolio includes high-speed SerDes, high-performance embedded TCAMs, ARM cores and performance and density-optimized embedded SR... » read more

Blog Review: Oct. 31
By Jesse Allen - 31 Oct, 2018 - Comments: 0

Mentor's Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results. Cadence's Paul McLellan explains DARPA's CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be. Synopsys' Sangeeta Kulkarni c... » read more

The Race To Design Larger Systems
By Ed Sperling - 25 Oct, 2018 - Comments: 0

For more than a decade, tools vendors and design houses have been talking about leveraging their tools and expertise to help design systems of systems. They're finally getting their chance. The basic idea behind this strategy has always been that issues inside any electronic system—performance, power, signal integrity, area—have all been dealt all the way down to the sub-atomic level in ... » read more

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