tag: Siemens EDA

The Week In Review: Design/IoT
By Jesse Allen - 10 Apr, 2015 - Comments: 0

Certifications TSMC certified a number of tools for its current 10nm FinFET design rules and SPICE models and 16nm FinFET Plus (16FF+) V1.0 process, including: Ansys' power integrity and electromigration tools; Cadence's custom/analog and digital implementation and signoff tools; Mentor Graphics' physical verification, design for manufacturing, and circuit verification tools; and Synopsys' ful... » read more

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

UPF 3.0 Moves Toward Ratification
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

The Power Estimation Challenge
By Lauro Rizzatti - 09 Apr, 2015 - Comments: 0

If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely power the top Android devices released in 2015. The story broke in early December along the lines that the 810 had problems with overheating. Whet... » read more

High-Performance Analog And RF Circuit Simulation Using The Analog FastSPICE Platform At Columbia University
By Mentor, a Siemens Business - 08 Apr, 2015 - Comments: 0

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Areas of research include design techniques for circuits operating below 1 V, digitally calibrated RF front ends for superior linearity performance, LO synthesizers for wireless applications,... » read more

Blog Review: April 8
By Jesse Allen - 08 Apr, 2015 - Comments: 0

No other human endeavor has seen such sustained exponential growth. But it's the end of an era for Moore's Law, says Cadence's Axel Scherer—and only the beginning of one for Moore's Law 2.0. Synopsys' Amit Sharma tackles the cache coherency extensions of the ARM Advanced eXtensible Interface (AXI) and points out that the infrastructure required for their verification needs to scale up in s... » read more

Week 43: Get Ready For A Sizzling DAC Pavilion
By Anne Cirkel - 03 Apr, 2015 - Comments: 0

We are having some fantastic spring weather here in Oregon. Check out the little video clip of my crazy dog Diesel at the Oregon Coast shot a few weeks back. Mind you, there is no ball in that chucker he’s dancing around for. That’s because, Kismet, my other dog you can see in the foreground, caught the ball and is bringing it to me, occasionally looking back over her shoulder at her somewh... » read more

Will Wearables Work Well Enough?
By Ed Sperling - 02 Apr, 2015 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler The rollout of the Apple Watch later this month has reset expectations for the wearable electronics market, just as early implementations of the Pebble, Fitbit and Google Glass helped raise awareness about a new level of portability and connectivity. Early projections are for strong sales, which in turn will propel a new level of connectedness for the ... » read more

The Electrifying Side Of AUTOSAR
By Mentor, a Siemens Business - 02 Apr, 2015 - Comments: 0

This paper describes a meta-model that covers specific portions of software-oriented AUTOSAR development methodology using the ECU Resource Template. Prior to actual software development, the standardized and open AUTOSAR meta-model can be used to develop an architecture. The ECU Resource Template is particularly well suited for such tasks, because it opens up the actual software-oriented AU... » read more

First Time Success and Cost Control
By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

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