Stacked die and fan-outs gain steam as shrinking features becomes more difficult. Where the biggest hurdles are and what’s being done about them.
After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up.
On one front, for example, a new wave of chips based on advanced 2.5D/3D stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP) and fan-outs.
“Industry momentum for advanced packaging has picked up,” said Sesh Ramaswami, managing director of packaging technologies and advanced product technology development at Applied Materials. “For stacked memory, there is momentum. For fan-out, we also see that the adoption is increasing. The technology and platform choice depends on the end application and derived value.”
Generally, though, many of these advanced package types are still in the early stages of production. To bring these technologies into the mainstream, the industry still faces some major challenges.
Bringing down the cost is perhaps the biggest challenge. “Each package type has a different challenge,” said Jan Vardaman, president of TechSearch International, a market research firm. “For each package type, yield is the key to lower cost. And yield is impacted by different factors in each case.”
To be sure, the manufacturing flow plays a key role in addressing both cost and yield. On that front, the advanced packaging manufacturing flow is progressing in some areas. But the industry is still wrestling with other parts of the flow, particularly the so-called mid-end of line (MEOL).
Some customers are already familiar with the issues. Many others are getting their arms around the problems. All customers will need to get a handle on the manufacturing issues in order to have more realistic expectations about their advanced packaging schedules.
To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps in advanced packaging.
Why advanced packaging?
Why do we need advanced stacked die and related packages? For one thing, IC scaling is becoming more difficult and expensive at each node. And it’s unclear how many foundry customers can afford to design chips at advanced nodes.
At the same time, planar DRAM continues to scale. But the industry is running up against a memory bandwidth wall, prompting the need for alternative solutions.
So, instead of traditional scaling, the idea is to go vertical. For years, in fact, the industry has been talking about the development of 2.5D and 3D chips using through-silicon vias (TSVs).
So far, though, 2.5D/3D technology is taking longer than expected to develop. As before, there are several challenges with the technology, such as cost, design complexities, logistics, thermal issues and a lack of standards.
More recently, though, the technology is making progress. Interposer costs have fallen in recent times. And advanced packaging is gaining steam. “TSVs are taking off where the applications demand it and can afford it,” said Ramakanth Alapati, director of packaging strategy and marketing at GlobalFoundries.
For example, Micron is sampling a stacked-memory technology, dubbed the Hybrid Memory Cube (HMC), for servers. Separately, SK Hynix is ramping up a 3D DRAM technology called High Bandwidth Memory (HBM).
And Samsung is developing HBM as well as its own 3D DRAM technology using TSVs. “If you take this through-silicon via idea, and you have thousands of through-silicon vias, you can create a very wide data path,” said Mike Williams, vice president of product planning at Samsung.
AMD, meanwhile, recently rolled out a 2.5D graphics chip. Rival Nvidia is developing a similar device.
And behind the scenes, the industry is working on a number of other advanced package types. “I was recently at an OSAT,” said Rezwan Lateef, general manager and vice president of lithography products at Ultratech. “They have 25 different types of packaging applications that they are trying to do. People are trying to figure out what is the right technology and equation. Again, it’s all based on cost.”
Still, the big question is clear: When will 2.5D/3D technology reach the mainstream? If it’s based on cost alone, 2.5D/3D devices could reach a cost-per-transistor parity with traditional chips at 7nm, according to experts. By 5nm, 2.5D/3D could have a 15% to 20% cost advantage, they added.
In any case, the industry is still several years away from bringing more complex 3D devices, such as logic-on-logic, into the market. “It makes sense to have logic-on-logic,” GlobalFoundries’ Alapati said. “But it’s not ready today or it’s not tomorrow.”
Meanwhile, the process flow for a given package depends on the technology. Generally, for 2D-based wafer-level package (WLP) types like fan-out, the wafer is first processed in the fab. Then, the wafer moves to the MEOL, followed by assembly and test.
The flow is similar for 2.5D/3D devices. The exception is that 2.5D/3D chips require TSVs, which are generally fabricated in the front-end-of-the-line (FEOL) or wafer fab.
In the wafer fab, the TSVs are fabricated using a via creation process. In this process, there are five main manufacturing steps: etch, CVD, PVD, electroplating and CMP. “TSV creation is not a bottleneck,” Applied’s Ramaswami said. “Costs have come down as equipment capability and productivity is picking up.”
In fact, the industry continues to make improvements in the TSV creation process. Traditionally, the industry has used the Bosch process, which is a switched gas technique. It involves alternate steps of isotropic etching with SF6 and a polymer deposition step with C4F8, according to Lam Research.
In a paper given at the recent ASMC event, Russell Dover, senior marketing manager at Lam Research, described a novel gas delivery technology, which is faster than the Bosch process. Lam’s rapidly alternating process (RAP) can increase TSV throughput by more than 200%.
After wafer processing and the TSV formation steps, the wafer is then sent to the MEOL. Fan-out and other wafer-level packages (WLP) are also sent from the fab to the MEOL.
The MEOL is situated between the front-end wafer fab and the traditional outsourced assembly and test (OSAT) house. In fact, the MEOL is where the lines are blurring between the IDM, foundry and the OSAT.
For example, the MEOL steps could take place in the IDM, foundry or Outsourced Semiconductor Assembly and Test. And for some time, the three entities have been competing with each other for the MEOL business.
The MEOL is also one of the bottlenecks in the flow. Some steps are more like front-end fab processes, presenting some issues for the OSATs. “(The MEOL) is a challenge,” said Calvin Cheung, vice president of business development and engineering for Advanced Semiconductor Engineering (ASE). “It requires a huge commitment. It’s not just resources or time, but also CapEx. Every single piece of processing equipment is new for 2.5D and 3D.”
Basically, the MEOL involves the following steps in order—copper pillar bumping; temporary bonding; wafer thinning; micro-bumping/redistribution line (RDL) processing; and de-bonding.
As stated above, the TSV creation process takes place in the wafer fab. At this point, the TSVs are embedded in the wafer. Then, in the MEOL process flow, the TSVs must be exposed or revealed outside the wafer to make the 2.5D/3D device. To reveal the TSVs, the wafer is thinned to a thickness of 50µm or less.
To thin a wafer, the substrate undergoes perhaps the hardest step in the flow—the temporary bonding/de-bonding process. This critical step prevents the wafer from breaking or warping during the flow. In the temporary bonding process, the wafer is flipped. A separate carrier wafer with an intermediate layer is temporarily bonded onto the main wafer.
Following that step, the main wafer undergoes a backside thinning process, which in turn exposes the TSVs. “The TSVs are embedded in thick silicon, close to 800µm. But a TSV is only 100µm. So that means we have to thin the wafer down to that thickness so we can expose the TSVs. That way, we can do connections and bumping. That’s a challenge. And you can’t use a high temperature process,” ASE’s Cheung said.
Then, using lithography, electroplating and other process steps, tiny microbumps are fabricated on the surface of the wafer. After that, the RDL lines and spaces are formed. Basically, the RDL lines re-route the signal paths to desired bump locations.
That’s not the big challenge. The hard part is the de-bonding process. The temporary carrier wafer and intermediate layer are de-bonded from the wafer. Historically, the temporary bonding/de-bonding tools have been slow and immature. But the latest tools in the market are much faster, according to Paul Lindner, executive technology director at EV Group.
“Temporary bonding and de-bonding is probably where yield improvements can still be made,” TechSearch’s Vardaman said. “For 3D-IC stacks, the de-bond process is seeing improvement, but the yields need to be higher. A combination of materials and equipment are required to solve this.”
In the MEOL, the delicate wafer handling issues are also cropping up in other packaging types. “The majority of the challenges are also in some of the new fan-out applications,” Ultratech’s Lateef said. “We are talking about substrates, or reconstituted wafers, that have their own challenges, such as warpage, thickness and weight.”
Also in the MEOL, the package must undergo several inspection steps. Inspection, the science of finding defects, is becoming more critical in packaging. In fact, killer defects are cropping up in the entire flow.
There are similarities and differences between inspection in the fab and in packaging. “It’s at a different scale, but it is a similar problem,” said Prashant Aji, senior technical director at KLA-Tencor. “You are not looking at 20nm or 10nm defects as in the fab, but rather you are looking at 2µm defects in packaging.”
For packaging, the industry uses macro defect inspection tools. “Detecting smaller defects is a key challenge,” said Elvino da Silveira, executive vice president and general manager at Rudolph Technologies. “Up until a couple of years ago, 3µm was a good macro inspection tool. But over the last couple of years, we have had a significant development project to inspect at the 1µm level.”
Then, after the MEOL process, the wafer moves to the final assembly and test steps at the OSAT. Test is complex. First, it requires built-in-self-test (BIST) engines within the chip. Then, in the test flow itself, the device requires several test insertion steps.
Still, despite the challenges and setbacks, advanced packaging is here to stay. “As Moore’s Law is slowing down, people are using the buzzwords ‘More than Moore’ and IoT. A lot of those are enabled by packaging,” KLA-Tencor’s Aji said.