More Choices, Less Certainty

Increasingly costly scaling is forcing the entire semiconductor industry to weigh options for what comes next.


The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades.

Those with deep enough resources and a clear need for density will likely follow Moore’s Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-beam e-beam, possibly in conjunction with directed self-assembly—to the impact of quantum effects, the availability and difficulty of working with new materials, and new transistor structures.

The current thinking among companies pushing toward smaller features is that there may not be a 10nm node. Some of that depends on who’s doing the counting, because one foundry’s 10nm can be different from another’s. But the overriding concern is that it’s taking too long for chipmakers to prepare for new nodes, so they’re skipping half-step nodes. This is the reason most companies ignored 20nm (despite the fact that two of the most popular application processors were developed at that node, and the 20nm BEOL process was extended to 16/14nm), and it will likely be true for 10nm.

“People who have been working on 10nm nodes say it is coming too fast for them to make their money back,” said Charlie Janac, chairman and CEO of Arteris. “At the same time, they are skeptical of any business case at 5nm. If you think about a carbon nanotube, that’s 2nm. So you have an interconnect equivalent to the width of three nanotubes. The cost becomes prohibitive. Most people are saying the economic game is up at 7nm, so they’re investing heavily in 7nm because they’re expecting it to last awhile.”

The 10nm node is considered a half-node, and half nodes traditionally have not been as long-lived as full nodes—130, 65, 28, 16/14 nm—which is why the big foundries are putting their efforts into 7nm instead of 10nm.

“You will get a little more than halfway at 10nm with power, performance and cost,” said Subramani Kengeri, vice president of global design solutions at GlobalFoundries. “The next full-node will be 7nm, which will be a very long node. Process nodes go through three phases: research, where they look at different materials, path-finding and development. Right now, 7nm has moved to the path-finding phase.”

Companies developing chips for servers, GPUs, smart phones and FPGA vendors will always push to the most advanced node available. What’s changed is that everyone else is no longer following them. Many chipmakers are weighing a dizzying array of other options, ranging from planar FD-SOI that could extend all the way to 10nm with double patterning, as well as 2.5D, fan-outs and monolithic 3D integration.

“What we’re seeing is a technology overlay,” said Mike Gianfagna, vice president of marketing at eSilicon. There are different technology flavors at different levels of maturity with different yield learnings. So with 2.5D, the number of options increases, but the certainty of the outcome goes down because of yield learning. There are not the years of yield learning that you have with planar silicon. But your reward can go up, too. It’s easier to divide and conquer but more difficult to package because the package is now more sophisticated. With FD-SOI, one discussion we’re having is that the data is quite different to look at. The biggest challenge we’ve dealt with is that there haven’t been as many of these shipped. And what is the roadmap for FD-SOI?”

Following the money
The question now is where the next round of R&D investments will go, and right now that answer depends upon whom you ask. Chipmaker consolidation and rising development costs costs may be in conflict if there aren’t the kinds of massive volumes driven by the boom years of PCs and smart phones. While smartphone shipments aren’t going down, the annual growth rates are slowing from about 10.4% per year in 2015 to 5.1% in 2019, according to IDC.

The smartphone market certainly will remain a huge driver of SoC growth for the foreseeable future. But as the market matures, devices will come under pricing pressure, which will in turn put pressure on the cost of developing SoCs for those devices. And with that market flattening, what else can generate the billions of units to continue driving Moore’s Law?

That question has been asked repeatedly in conferences over the past year. While the answer is clear enough—nothing right now—chipmakers are taking a second look at whether the question is even relevant anymore.

“It’s the profit that counts,” said Steve Carlson, group marketing director in Cadence‘s Office of Chief Strategy. “Systems companies are taking designs in-house, and we’re seeing more re-aggregation through M&A and organic growth. So the semiconductor cost may increase, but the price of the system may decrease. That isn’t just dependent on the bill of materials. It’s also assembly, test and reliability. We’re seeing product planning that is much more comprehensive and scientific. So while some companies are spending more on semiconductors, the total cost of the product across the product lifecycle is going down.”

This raises some interesting issues for the semiconductor market, though. One of the key factors in reducing the cost of chips in particular, and electronics in general, is economies of scale. Historically, feature shrinks and a market could drive huge volumes at each new node allowed foundries to invest in new processes—and EDA tools, IP and manufacturing equipment to generate revenue by taking advantage of those processes.

At 28nm and below, each foundry’s process is different, which means tools, IP and some equipment have to be customized. And below 16/14nm, there are many more uncertainties than ever before, such as when EUV or multi-beam e-beam lithography will be commercially viable, how many colors will be needed for how many photomask layers, and whether new materials will be needed to reduce RC delay, how difficult they are to work with, and how they will affect cost. The list goes on and on, which from a high level helps explain why foundries are pushing to smaller geometries faster than in the past. They can’t afford to invest in half-nodes that won’t get enough traffic to warrant their investments.

Changing business dynamics
Not everyone is pushing in the same direction, though. The emphasis on getting to the next process node is waning as more options come to market. One of those options is fully depleted silicon on insulator. Samsung, STMicroelectronics, Leti and GlobalFoundries all are pushing FD-SOI as an alternative for chipmakers that don’t need the density finFET-based solutions can provide. In the case of 28nm FD-SOI, leakage current is comparable to a finFET at 16/14nm. At 22nm, GlobalFoundries and STMicroelectronics say performance and leakage are comparable to finFETs.

What isn’t clear yet is just how competitive FD-SOI will remain with 3D transistors the next nodes after 16/14nm, and part of the issue there has to do with lithography choices and what becomes available at what time. GlobalFoundries is considering a 10nm planar FD-SOI chip, for example, which would not require double patterning or finFETs—particularly with new Lithography.

“The design infrastructure for 10nm and 7nm is really expensive,” said GlobalFoundries’ Kengeri. “The cycle time is longer because you have 60 to 70 masks, and to ramp a product from tapeout to production is more difficult. That makes 10/7nm riskier than 22nm FD-SOI.”

The 22nm node has the added benefit of being the last node for single patterning, and FD-SOI uses planar transistors plus body biasing to achieve lower power.

“With FD-SOI, the data is quite different to look at,” said eSilicon’s Gianfagna. “The biggest challenge that technology faces is how many have been shipped and what is the road map for FD-SOI. The market loves options, but has FD-SOI overtaken finFETs? No.”

Rethinking older nodes
The hedge strategy here involves fan-outs and 2.5D, and it may prove to be much more than just a hedge. TSMC‘s fan-out business, called InFo, for Integrated Fan-Out, is growing steadily, according to multiple industry sources. Companies such as HiSilicon, ASE Group and Marvell are developing commercial implementations of 2.5D chips, and Huawei, IBM and AMD are selling them. (Intel is developing its own stacked die technology, although timing for introduction of this technology is not yet determined.)

“Ultimately, the world has no choice but to go 3D,” said Janac. “When that happens, the packaging houses become very important. The issues for each chip becomes how you guarantee the package will work. Testability has to be put into the interconnect, which means the packaging houses also become design houses.”

Whether that packaging is done by Outsourced Semiconductor Assembly and Test or foundries remains to be seen. Both are positioning themselves to be able to take advantage of that shift. And with that shift comes a renewed interest in established nodes, which reach far beyond just a monolithic older-node device. With interposers, bridges, and even through-silicon vias, the problems of RC delay largely disappear. What has held this back until now, though, has been a concern about price, and that has largely disappeared.

“2.5D and fan-outs have hits a new price plateau over the six months or so,” said Carlson. “There has been more than a 50% step-down in cost. That opens up a lot more avenues for creativity. It’s not just about the next node. Power and performance envelopes are not getting much better under more complex architectures. At the same time the number of packaging choices have grown. You can contemplate this for multiple products so that they are architected and packaged so there is good profitability.”

This is harder than it sounds, which is a key reason why it has taken so long for 2.5D to begin rolling out commercially. “It’s about packaging, architecture, and how you lay it all out on silicon,” said Calvin Cheung, vice president of business development and engineering at ASE. “We’ve been working closely with partners on this. The interconnect can be up to a few thousand bumps or microbumps, and you have to make every one is connected. That requires you to get the right materials and equipment, and you have to understand how to pick the right piece of equipment.”

But as those problems are being solved, the price is dropping fast. GlobalFoundries’ Kengeri says there are three main markets for 2.5D. The first involves splitting larger die into multiple parts to improve yield. The second is optimizing functions for each chip or module within a package, which is the approach that Marvell, ASE and Tezzaron have taken. The third involves chips with either huge amounts of memory, which can be split off into separate parts and connected through an interposer.

All of the major foundries are positioned to utilize any of these approaches, whether it’s gate-all-around FETs, horizontal or vertical nanowire FETs, 2.5D, full 3D-IC, monolithic 3D-ICs or fan-outs. GlobalFoundries and Samsung are backing FD-SOI. And the OSATs are positioned to take advantage of any advanced packaging options. As research continues to evolve, they’re actively trying to stay current with the market, and the market is trying to stay current with them and figure out the best way(s) forward.

This is like trying to build a platform on a moving foundation, though. At some point choices will need to be made, whether they’re for the next big thing or lots of smaller things that are connected together. As Kengeri observed, “Five years from now, everything will have a radio. Whether that will be very advanced logic or planar FDX (FD-SOI) or 2.5D remains to be seen. But all of them will need to be done at very low cost.”

  • memister

    The more you skip, the longer it takes to develop the next step..

  • Ed Sperling

    Memister, you’re right about that, but it isn’t so clear what the next step will be. What do you think about quad- or octa-patterning with EUV?

    • memister

      I think 2 double patterning techniques may be combined for immersion since they’re getting cheaper. 10 nm widths or less, the gates can’t stop tunneling.