New architectures, business models and packaging are driving big changes in chip design and manufacturing.
Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry.
While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are forcing the industry to slow down. For one thing, there are fewer “fast followers” due to consolidation over the past couple of years. In addition, the cost of migrating to the next node is prohibitive for an increasing number of applications, particularly in light of the diminishing returns on power and performance.
This is evident in TSMC’s earnings reports, which show a general downward trend for revenue obtained from advanced nodes over the past eight years. TSMC is by far the largest foundry with 54.3% market share, according to Gartner, although it is not the only foundry manufacturing chips at the latest process nodes, or the only one seeing this shift.
This doesn’t mean business at those nodes is slipping in real dollars, but it does indicate more activity for longer periods of time at all process nodes. All of the major foundries have recognized this, adding low-power and high-performance versions of processes at well-established nodes, as well as specialized processes that provide additional revenue sources.
Even Intel, which has been an unwavering proponent of Moore’s Law and its two-year cadence, said last week it will increase the amount of time between nodes—essentially turning the “Tick-Tock” strategy it defined at the turn of the Millennium into Tick-Tock-Tock.
“Moore’s Law is slowing down,” observed Kelvin Low, senior director of foundry marketing at Samsung. “We definitely see it becoming more challenging. Cost will be a huge factor. It will be more costly to develop new processes, and more costly to develop fabs. Rock’s Law says that the cost of building a new fab doubles every four years.”
Plenty of options for most companies
While this may limit how quickly advanced processor and large FPGA vendors move forward, for the vast majority of semiconductor companies the decision about what to do after 28nm is still several years out. Many chips, particularly analog, are being developed at 250nm or larger. Mainstream chips for the IoT, automotive, and a number of other vertical markets currently are somewhere between 130nm and 40nm. Even for chipmakers working at 40nm, 28nm is just one more shrink along a well-defined path, with the same economies of scale and power/performance improvements that previous nodes provided. The 28nm node still uses planar transistors, rather than finFETs, and only requires single patterning.
“The necessity for moving to 28nm, and 28nm pricing, is still high,” said Walter Ng, vice president of business management at UMC. “In fact, the migration pace is increasing. We’re also seeing a lot more demand for capacity at 55/40nm, and the pricing is looking more palatable to a wider number of applications.”
Meanwhile, GlobalFoundries and Samsung have developed 28nm FD-SOI planar processes to control current leakage, which has been a persistent design issue after 55nm. GlobalFoundries introduced a 22nm FD-SOI process, as well, adding another planar node that can limit leakage using forward and back biasing, with a performance boost over 28nm FD-SOI. GlobalFoundries said it also plans to add one more planar node somewhere in the 12nm to 14nm range at some as-yet undetermined date.
“There are a ton of people still back at 40nm and 28nm who haven’t made a decision about where they’re going to go,” said Gary Patton, chief technology officer at GlobalFoundries. “They could go with finFETs, which do offer good performance. But they’re locking themselves into something with high design costs and high complexity. Or they can take the FD-SOI route. That’s much easier to design in at a lower cost point.”
Betting on packaging
These pre-finFET nodes are where many of the new application opportunities are cropping up, as well. The emphasis is on cost, time-to-market, and highly customizable designs. In addition, these chips are being developed in much smaller batches—thousands or millions, rather than hundreds of millions—which is why there is so much attention on multi-chip packaging approaches and methodologies. The goal is to mix and match chips or “tiles” developed at different process nodes. So while 22nm FD-SOI, and 28nm CMOS, are the last nodes before finFETs and double patterning, that still leaves most chipmakers with plenty of options well into the next decade without ever having to venture into the finFET world.
“Packaging in multi-die solutions is gaining steam,” said Ng. “And it has a potential for gaining a lot more steam if the cost points come down a little. We are on the cusp of packaging solutions that will open up the ability for more applications to take advantage of multi-die packaging. There is a lot of integration going on already, both for time-to-market reasons as well as economic reasons. We believe that in the next few years, 2.5D and other solutions will be much more mainstream.”
Numerous other companies agree. Marvell has bet heavily on multi-chip packaging as a future direction with its MoChi mix-and-match architecture because the economics of scaling no longer work for many applications. “It costs $300 million to develop a new SoC at 16/14nm,” said Zining Wu, CTO at Marvell. “Each chip will have to sell in volumes of 100 million just to break even.”
That math hasn’t been lost on the foundries. “With system-level performance scaling every generation, the costs go up due to complexity and the lead time takes longer,” said Samsung’s Low. “High mobility materials can help, although there will be tradeoffs. So can system architectures, where you look at the problem in a different way and not just rely on silicon technology. You partition the system to achieve system-level performance scaling. With 2.5D and HBM-2, system-level performance increases, but the process technology does not shoot up as much as with other approaches because you can partition the problems.”
Fan-out packaging also may be poised to turn a corner, according to a just-released report from Yole Développement. The research house said Apple’s adoption of TSMC’s Integrated Fan-Out (InFO) for its 10-application iPhone 7 could draw new players into that approach.
Stacked memory, such as high-bandwidth memory, is a potential game changer for multi-chip packages. It has several key advantages over standard dual in-line memory modules, which are a staple of existing compute architectures. The first generation of HBM DRAM supported a transfer rate of 128 gigabytes per second. HBM-2, introduced this year by Samsung and SK Hynix, is twice as fast, with enormous capacity potential in stacked configurations.
Perhaps even more important, it is a JEDEC standard (JESD235) and can be manufactured using existing CMOS processes, so it is expected to be able to achieve the same kinds of economies of scale that have defined DIMMs. Coupled with a less expensive interposer or some other interconnect, the price of multi-chip packaging could drop significantly. Until now, 2.5D packaging has been confined to relatively price-insensitive applications, such as enterprise networking switches and processors made by companies such as Cisco, Huawei, IBM and AMD, but if the prices drop sufficiently this could become a mainstream option.
“The von Neumann architecture is 80 years old, and it presumes that every computation will pull data from memory, process it, and then send it back to memory,” said Steve Teig, CTO of Tessera. “The von Neumann bottleneck is area, cost, power and throughput. This allows us to finally get beyond the von Neumann architecture.”
Other stacked memory types attempt to tackle the same problem. Micron’s Hybrid Memory Cube uses multiple layers on logic, connected by through-silicon vias. There also is 3D NAND for storage. But for off-chip memory, between SRAM and storage, it’s hard to beat the economies of DRAM, which is why HBM has garnered so much interest.
Future foundry directions
Put all these pieces together and it’s not hard to see why foundries, as well as OSATs such as ASE and Amkor, are promoting advanced packaging. TSMC’s InFO is a step in this direction, but the real performance and power improvements will come with economies of scale in 2.1D (organic interposer), 2.5D (silicon interposer), and monolithic 3D.
The upfront investment for the entire supply chain is significantly lower, as well. The cost of developing a next-generation process at the most advanced nodes is estimated at $1 billion, according to industry sources. The cost of building an advanced fab at the most advanced nodes is somewhere around $14 billion. And the return on investment becomes much less certain as the mobility market flattens and fewer companies develop fewer designs at the most advanced nodes.
When questioned, foundries tend to be cagey on this issue. There are no clear answers about ROI, and chipmakers developing high-volume chips at the most advanced nodes routinely play off one foundry against another to get the best pricing. As the number of chipmakers competing in this space shrinks, those economics become even more strained.
Compare that with older nodes, where equipment and fabs are already fully depreciated and processes are stable, and the picture looks much different, even if it is somewhat convoluted. There are still a number of variables to consider on all sides, including green initiatives, according to Joanne Itow, managing director for manufacturing at Semico Research.
“Operational savings from reductions in energy costs, lower chemical usage, reduced cleaning solvents, recovering and recycling materials such as water/gases/chemicals, look great for an environmental/social conscious strategy, but in addition it saves multi-millions of dollars. That helps to keep the break-even point from exploding out of reach. Type of product, management of equipment idle time, modular production lines and a number of other things impact fab operational feasibility even if capacity utilization isn’t at 90%. In general, capacity utilization at leading-edge fabs have gone up just because, other than advanced memories, the foundries are carrying the brunt of the load.”
What this points to is a very complex business model in the future, requiring nimbleness in a part of the market that for years has been somewhat lumbering.
“The ability to pull together different skill sets is becoming more of an advantage,” UMC’s Ng observed. “The key is the ability to isolate different pieces of a solution. That way you can optimize which piece of a module has to run at the highest performance to create the biggest bang. If you don’t have to touch a piece there is less risk, so you have to look at these modules at a system level.”
It’s not just chipmakers that are evaluating which way to go next. Using metrics such as performance per watt, throughput to memory, and operations per second, device scaling alone no longer wins the race at the most advanced nodes. And as the number of companies looking to shrink features continues to shrink itself, the economics of scaling will become less attractive to more companies.
None of this will cause sudden shifts because development cycles for complex chips are still at least 18 months, and in many cases more than twice that. Nevertheless, it’s hard to argue that node progressions are slowing. That could open the door for chipmakers working at advanced nodes to commercially offer platforms developed at the latest nodes for other vendors’ multi-chip packages. It also raises the possibility that the number of foundries working at the most advanced nodes will shrink, particularly as the cost of developing IP rises beyond the means of IP companies to support all of the latest nodes.
But for the first time in decades, all options are on the table and many more are in research—and no one is brushing them aside.
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