New FETs, qubits, neuromorphic approaches, and advanced packaging.
The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works.
Semiconductor Engineering sat down to discuss these technologies with Marie Semeria, chief executive of Leti; An Steegen, executive vice president of semiconductor technology and systems at Imec; and An Chen, executive director of the Nanoelectronics Research Initiative (NRI) at the Semiconductor Research Corp. (SRC). (Chen is on assignment from IBM.) What follows are excerpts of those conversations.
SE: What are some of the bigger issues with chip scaling?
Steegen: Of course, one of the big questions that you typically get about advanced technology nodes is this: Why are we still developing these costly nodes and what is the cost associated with these advanced technology nodes? For one thing, there is an explosion of data. Many applications, such as social media, generate a lot of data. We have to make sure that we don’t end up in a data deluge. If we don’t provide technology and systems solutions for these technology platforms, you are going to end up with server farms the size of Manhattan.
Chen: The lithography challenges are still there. Now, if EUV proves to be a production solution, that’s great. We can probably go longer on the scaling path. Overall, lithography is still a big problem. In addition, the power dissipation (in devices) is still a big factor that we have to contain. That’s why people are looking for these new steep slope or low-power devices.
SE: For now, IDMs like Intel may extend finFETs to the full-scaled 7nm node. Then, they are evaluating various transistor options at the full-scaled 5nm node. Meanwhile, foundries are following a more relaxed version of the nodes. Basically, a “foundry 5nm” resembles a full-scaled 7nm. And a “foundry 3nm” or so-called “5nm plus” may resemble a full-scaled 5nm. Regardless, at this point, the industry is evaluating the following technologies—finFETs; lateral gate-all-around FETs or nanowire FETs; and nanosheet FETs. How will this all play out?
Steegen: The candidates are still there. What always happens, and what will continue to happen, is that companies are going to try to stretch what they have until it really breaks. The big question is the finFET. How long is the finFET going to last? A little incremental improvement there with new materials or the relaxation of the gate length is likely going to give your fin one extra life. Then, there are those who want to extend the finFET or relax the dimensions. This will be determined by gate length scaling. If you stop your gate length scaling, certainly you can extend your fin. But what density gain do you get. That’s why the finFET-to-nanowire transition is something for 5nm. You are going see a ‘5nm-plus’ with a nanowire.
Semeria: We are pushing FD-SOI to 10nm. Then, we made the comparison between finFETs, FD-SOI and nanowires. We found that nanowires show better results than finFETs and FD-SOI. It’s the reason why we switched to stacked nanowires, particularly for 7nm, 5nm and down to 3nm. We are able to narrow the wire down to 3nm. So this technology could be pushed probably down to 3nm. Nanowires can be on SOI or on bulk.
SE: Gate-all-around FET, or nanowire FET, is basically a finFET on its side with a gate wrapped around it. What are the challenges here?
Steegen: First, you need to prove the device feasibility. We have sufficient data that shows you have better short-channel control. You have a smaller gate length. Now, there are the integration details like how to integrate these nanowires in a process control way and how to shut down all of the parasitic leakage paths. There are no showstoppers there. A nanowire process might look disruptive, but it’s an evolution of a finFET. For designers, they won’t see the difference.
Semeria: The question is the variability and the manufacturability of such a process and structure. We have to manage the stress in the process in order to boost the performance. We need to control the integration in order to control the variability. Regarding nanowires, we need very advanced characterization tools in order to control the local strain all around the nanowire.
SE: What about the channel materials for the initial nanowire FETs?
Steegen: They are silicon. You can do it in germanium, maybe some silicon germanium in the PFET.
SE: The nanosheet FET is like a gate-all-round FET, but the nanowires are thicker. Any thoughts?
Steegen: When we say nanowire, it can be any shape or form of a fin. It can be like a pancake or a sheet. It can be a nanowire like we typically show. So there are a few flavors.
SE: What’s next in advanced packaging?
Steegen: We will likely see some diversification. You will see new technology platforms. They may be beneficial for certain functions, but you are likely not going to do this for a full SoC. So, you are starting to talk about hybridization. You need to start stacking the dies or you need advanced packages to fold various technologies together.
Semeria: 3D integration is key. At the end of the roadmap, you will see stacking using 3D. For example, we introduced the CoolCube, which is monolithic 3D integration. It’s quite generic. It’s relevant when you need very high dense vertical interconnects. We are seeing interest for CoolCube technology in order to implement memory close to CMOS.
SE: Leti and others are also exploring the concept of chiplets. Chiplets are discrete components of an SoC. But rather than putting everything on one die, they are developed separately for inclusion in a package. Why is the industry looking at this?
Semeria: It’s very flexible. You can add more and more functions at the interposer level. With chiplets, you have the flexibility to choose the right IP. You have more options with the partitioning.
SE: Let’s move back to device scaling. CMOS may scale to 5nm. Then, at 3nm, it becomes cloudy. There are a number of options on the table. Or perhaps CMOS scaling will run out of steam. What will happen at 3nm?
Steegen: We will definitely see two generations of nanowires (starting at 5nm). So you could squeeze in another generation of horizontal nanowires.
Semeria: We can introduce nanowires as soon as 7nm. And then push them to 3nm perhaps.
SE: There are other options at 3nm and beyond. For this, you might have the more traditional CMOS devices like nanowires or futuristic technologies. Any thoughts here?
Steegen: We are looking at other stuff. Vertical nanowires is one. Stacked devices are another. The beyond-CMOS switches like tunnel FETs and all of those are back on the table. Complementary FETs could be the next one after the lateral nanowire. When you have a nanowire, you have NFETs and PFETs. In complementary FETs, you put NFET on the PFET. The question there is the process flow. That one needs to be thought through.
Semeria: TFETs and nanowires are good candidates for high performance and low power.
Chen: There are options like tunnel FETs. There are also some other novel concepts like negative capacitive FETs. Those new concepts are targeting one fundamental problem that FETs have. That’s the slope. They call that the 60-millivolt-per-decade slope. That’s the limit. So people are trying to go over that barrier by introducing some new mechanisms. In principal, those new mechanisms do provide you a steeper slope. However, they also bring in a lot of unexpected and non-ideal factors. So eventually, the overall performance of those devices is not better. For example, in tunnel FETs, you can see the steep slope at the low current region. But at the high current region, the on current is very limited. For the negative capacitance FET, there are different issues. And that is a pretty new concept that has not been proven completely from the feasibility point of view.
SE: In addition, the industry has been working on post-CMOS logic devices like spin-wave and spintronics. What about those?
Chen: If we go broader than a drop-in replacement for CMOS, then we can talk about memory-like devices or spintronic devices. All of those different kinds of devices are far from a drop-in replacement. They operate differently. They have different structures. They are fabricated differently. So if we want to replace CMOS, instead of having a drop-in replacement for FETs, those devices have to be proven significantly better in terms of their economic feasibility. All of those devices have not shown us any kind of benefit at that level to justify that kind of investment. As a matter of fact, a lot of those novel devices were shown to be poorer than CMOS FETs, especially in terms of speed.
SE: What’s the bottom line here?
Chen: Five years ago, I was on a panel that talked about life beyond CMOS. All panelists agreed that we were not going to replace CMOS. Now, it’s more likely we are going to augment CMOS by using those devices. People are looking at a different way of utilizing those devices now.
SE: So basically, the industry hasn’t given up on TFETs, NC FETs, spin-wave and other futuristic technologies. In 2018, the SRC will start a new program called nCORE. What’s that about?
Chen: The NRI program is looking at CMOS replacements, and later, CMOS augmenting device technologies. The nCORE program is looking at materials, device and interconnect solutions to enable new computing paradigms. If you look at what categories of devices we are looking at (within nCore), steep devices is one. TFETs and NC FETs are still in our scope. Oscillator devices are another. Another category is logic switches with non-volatility. That means you can combine logic and memory together. Spin devices are mainly in the category of logic switches with memory. Then, you have devices for neuromorphic.
SE: Let’s move to neuromorphic technology. Facebook, Google and others have developed systems using machine learning. Basically, these systems use neural networks. In a neural network, the system crunches the data and identifies patterns. Over time, it learns which of those attributes are important. Meanwhile, neuromorphic computing uses specialized hardware to enable machine learning. Where are we in this field today?
Chen: A lot of neuromorphic computing today is implemented on a GPU, a general purpose GPU or GPGPU. GPUs are designed for matrix computations, which is the main part of the graphics process. A lot of deep learning or neural network designs are also matrix computations. So they utilize a GPU very efficiently. Now, can you do better than the GPU itself? People are doing research in devices like memristors. Some use the name ReRAM or oxide-based switches. A lot of those devices have analog behaviors. If we can use those devices to implement synaptic behaviors in a neural network, they can be much denser than a GPU. They can be naturally tuned for those neural network algorithms. That’s a direction we are looking into.
Semeria: The software is available today for neural networks. You can apply the software to solve some cases like face recognition. It’s a software-only solution. We are working on an implementation of a neuromorphic approach at the hardware level using OxRAM. It’s a way to implement a neuromorphic approach using the synaptic behavior of OxRAM. It’s much more powerful.
SE: Basically, neuromorphic chips are fast pattern-matching engines that process the data in the memory. The first neuromorphic-class chips are based on SRAMs, which have limited programming capabilities. The next wave of neuromorphic chips is moving towards phase-change and ReRAM. OxRAM is a type of ReRAM. Any thoughts here?
Semeria: Neuromorphic hardware is much more efficient in terms of pattern recognition.
Chen: The next step is to make those programmable synaptic devices. Phase-change memory is more mature than ReRAM. But there are still a lot of issues with phase-change memory to implement those synaptic behaviors. ReRAM is another variety of a memory device that you could utilize to implement a synaptic behavior. But they face even more problems than phase-change memory. Basically, you need a well-controlled analog behavior of those memory devices. But these memory devices are not really designed as an analog device. They are designed for digital. For multi-level cell (devices), you probably need 4, 8 or 16 layers. But in neuromorphic systems, you need sometimes many hundreds of levels that are well controlled. Implementing those on one device has been demonstrated. But you need a neural network with thousands or even millions of devices. Demonstrating this kind of behavior on a large array is extremely difficult.
SE: Let’s talk about quantum computing. In classical computing, the information is stored in bits, which can be either a “0” or “1”. In quantum computing, information is stored in quantum bits, or qubits, which can exist as a “0” or “1” or a combination of both. The superposition state enables a quantum computer to perform millions of calculations at once. Where does quantum computing fit?
Semeria: Quantum computing could be very efficient if you need to check many different possibilities in parallel.
Chen: There is a lot of funding going into that type of research. If it succeeds, it’s definitely a game changer.
SE: Startup D-Wave has shipped a quantum computer and recently demonstrated a 2,000-qubit processor. In addition, IBM and several governments are also developing the technology. Today’s systems run relatively basic algorithms, however. The ultimate goal is to develop a full-scale, “universal” quantum computer, which could crack the world’s most complex algorithms and codes within a reasonable time. How far away are we from a “universal” quantum computer?
Semeria: Probably, the first applications at the software level are within the next five years. But the implementation of the technology will require more than ten years.
Chen: I am pretty hopeful that the industry can come out with something we can commercialize in the future, even if we don’t see a complete quantum computer. Different varieties of technologies can come out of that, like quantum communications and quantum sensing.
SE: D-Wave’s technology makes use of superconducting devices. IBM is pursuing a quantum computer using Josephson junctions, which are also based on superconductors. In contrast, Intel, Leti and others are exploring the use of silicon to enable quantum computing. How will this all play out?
Semeria: It’s the same thing regarding neuromorphic computing. First, there might be a software approach to solve a problem. And then, you will have an implementation in silicon. This will take more time. It could be based on nanowires. We demonstrated that using silicon-28, which is an isotope of silicon. We can get enough current to demonstrate qubit gates. It’s the first demonstration proven on silicon. It’s compatible with CMOS. In our case, it’s more like spin engineering using the properties of silicon. It’s a new integration scheme in order to be able to play with the spin. You need the confinement of the nanowires. You need some double gate architectures. But you also need a way to enable spin in these architectures and maintain the currents. And then we have to fabricate these devices in large scale. We are just in the beginning here.
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