Data Feed Forward And How It Works: Part 1


With data analytics, manufacturers can gain unparalleled insights into their testing processes, identify patterns, predict failures, and optimize operations. From improving yield rates to reducing testing costs, data analytics not only enhance the quality of semiconductor devices but also drives innovation and competitiveness in the industry. Traditionally, data analytics has been performed ... » read more

Test Hyperconvergence In Semiconductor Development


Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who developed a set of test patterns for the manufacturing floor. As this process became more automated and chips became more complicated, test considerations crept into the development flow and design-... » read more

Chiplet Interfaces Embrace Failures


Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

Redefining Sustainability: Operational Resilience Is the New Frontier


Powering everything from smartphones, energy infrastructure, electric transport, and AI systems, semiconductors have become a cornerstone of economic innovation. However, rapid progress has an impact. One recent survey shows that the semiconductor device manufacturing industry more than doubled its annual electricity consumption between 2015 and 2023 – an increase of 125% during that period. ... » read more

Optimizing System Production with On-Chip Telemetry and ML-Driven Analytics


Abstract As system companies integrate increasingly advanced chips onto their boards for high-performance markets such as AI, Cloud, Telecommunications, and Automotive, the complexity of system production continues to rise. Ensuring quality, performance, and lifetime reliability while minimizing test costs and production time has become a significant challenge.‍ A new solution addres... » read more

SLM: Actionable Silicon Insights Through Intelligent Measurement and Analysis


Developing semiconductors has always been a complex process, with advancements in electronic design automation (EDA) tools and fabrication technologies working to meet growing demands for larger designs, improved power efficiency, and better performance. As chip and system complexity increases alongside higher expectations for product reliability and longevity, traditional methods are reaching ... » read more

End-to-End Yield Management for Compound Semiconductors Manufacturing


Abstract: Progress in compound semiconductors is hindered by the high level of defectivity of the initial material. Here we take Silicon Carbide manufacturing technology as an example and provide an overview of manufacturing analytics tools and methodologies used to drive yield ramp and capacity expansion. We focus on 2 examples of site-to-site handoff: substrates handoff to IC front-end fab or... » read more

New Error Correcting Code And Non-Volatile Memory Options For Memory BIST


Tessent MemoryBIST from Siemens EDA provides a complete solution for at-speed test, diagnosis, repair, debug and characterization of embedded memories. Leveraging a flexible hierarchical architecture, built-in self-test (BIST) and self-repair can be integrated at both the individual core level and the top level. Tessent MemoryBIST efficiently addresses the ever-increasing demand for testing ... » read more

Issues In Ramping Advanced Packaging


Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entir... » read more

Changes In Scan Test Data


Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

← Older posts Newer posts →