Probing From Home


The current stay-at-home, work-from-home situation challenges the semiconductor industry in a way we have never seen before. Social distancing and remote work put operational procedures in place that can be difficult. In a previous post, we shared information on our virtual demos designed to help keep your semiconductor measurements running no matter where you are physically located. In this ... » read more

Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Monitoring IC Abnormalities Before Failures


The rising complexities of semiconductor processes and design are driving an increasing use of on-chip monitors to support data analytics from an IC’s birth through its end of life — no matter how long that projected lifespan. Engineers have long used on-chip circuitry to assist with manufacturing test, silicon debug and failure analysis. Providing visibility and controllability of inter... » read more

Adopting Yield Analysis Tools


DisplayLink is a fast growing medium-sized semiconductor fabless company from Cambridge UK. We began working with them a few years ago. We caught up with Shane Zhang, Head of Product Engineering to find out why he works with yieldHUB, the problems we solve and the features he likes most. Tell us about DisplayLink. Our operations team is based in Cambridge, UK. We work with teams, suppli... » read more

Design And Measurement Requirements For Short Flow Test Arrays To Characterize Emerging Memories


Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycle and high wafer cost. We propose a short-flow based characterization of Memory Arrays using a Cross Point Array approach. A detail analysis of design requirements and testability confirms feas... » read more

Test Setup Optimization And Automation For Accurate Silicon Photonics Wafer Acceptance Production Tests


Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and... » read more

Data Becomes Key For Next-Gen Chips


Data has become vital to understanding the useful life of a semiconductor — and the knowledge gleaned is key to staying competitive beyond Moore’s Law. What's changed is a growing reliance earlier in the design cycle on multiple sources of data, including some from further right in the design-through-manufacturing flow. While this holistic approach may seem logical enough, the semiconduc... » read more

RMAs: Root Problem Found


For decades, costs of production and maintenance have been driven down through manufacturing, process and logistical innovation, creating more breathing room for margin to maintain viable growth. There are other costs, however, that we seemingly accept as inevitable and simply get better at factoring in as par-for-the-course, or ‘eggs broken’ to make the omelet. The ubiquitous presence of ... » read more

Using ML In Manufacturing


How to prevent early life failures by applying machine learning to different use cases, and how to interpret models for different tradeoffs on reliability. Jeff David, vice president of AI solutions at PDF Solutions, digs down into how to utilize data to improve reliability. » read more

How To Improve DPPM By 10X Without Affecting Yield


Chips today are under immense pressure. With wider process variation manifested at wafer and die levels in single-digit nodes, highly complex designs, and effects of application and system integration, it’s no wonder the electronics value chain is becoming ever more reliant on expensive guard-bands. The ecosystem is not yet equipped to find all existing defects during test. So while quality e... » read more

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