category: System-Level Design

category: Auto, Security & Edge AI

Plan-Based Analog Verification Methodology
By Cadence - 27 Apr, 2016 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifie... » read more

Analog-To-Digital Conversion Is Key For Deep Space Exploration With The James Webb Space Telescope
By Mentor, a Siemens Business - 27 Apr, 2016 - Comments: 0

Reflect back to your last design project. Did it have leading-edge requirements that seemed impossible at the time to fulfill? Now think about a design that needs to live in the harsh environment of space. A device that has to sip power and function flawlessly for over a decade because there is no opportunity to service it if anything goes wrong. That is the set of requirements that faced Dr. L... » read more

Securing The Internet of Things Using Hardware Rooted Processor Security — An Architect’s Guide
By Synopsys - 27 Apr, 2016 - Comments: 0

Security is a key requirement for Internet of Things (IoT) devices and must be considered for all aspects of the design. This paper provides an overview of security basics, feature requirements, technical solutions, and associated system-level trade-offs for implementing security in IoT devices. Making the required trade-offs is significantly easier by leveraging secure, proven building blocks ... » read more

SoC Verification Made Easy
By Aldec - 27 Apr, 2016 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, there-fore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This docu... » read more

Automating Front-End SoC Design With NetSpeed’s On-Chip-Network IP
By NetSpeed Systems - 27 Apr, 2016 - Comments: 0

This white paper from The Linley Group examines the challenges of turning SoC architecture specifications into successful design implementations. It presents the case that SoCs are becoming too large and complex for existing design methodologies and identifies the need for a more automated front-end design process. To read more, click here. » read more

Blog Review: April 27
By Jesse Allen - 27 Apr, 2016 - Comments: 0

In a video, Cadence's Chris Rowan looks at the future of neural networks, particularly the shift from cloud-based to embedded devices and what we can increasingly expect from them. Waiting for RTL? Mentor's Rich Edelman suggests a way to get tests that are missing some simple RTL running with a bit of SystemVerilog. Synopsys' Richard Solomon provides a primer on calculating the bandwidth ... » read more

Formal Verification Applied To The Renesas MCU Design Platform Using OneSpin Tools
By OneSpin Solutions - 27 Apr, 2016 - Comments: 0

An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 26 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

System Bits: April 26
By Ann Mutschler - 26 Apr, 2016 - Comments: 0

Reconfigured Tesla coil electrifies materials In a development that could set a clear path toward scalable assembly of nanotubes from the bottom up, Rice University researchers have discovered that the strong force field emitted by a Tesla coil causes carbon nanotubes to self-assemble into long wires, a phenomenon they call Teslaphoresis. Rice chemist Paul Cherukuri led the team that develo... » read more

The Week In Review: Design/IoT
By Jesse Allen - 22 Apr, 2016 - Comments: 0

Tools Rambus released the latest version of its platform for analysis of power and electromagnetic side-channel attacks, featuring upgrades to the workstation software and user interface for enhanced system performance and usability in ASIC and FPGA side-channel vulnerability testing. Deals Istuary Innovation Group licensed Arteris' FlexNoC interconnect IP for enterprise storage contro... » read more

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