category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2023 - Comments: 0

Synopsys' John Swanson and Manmeet Walia note that designing for 224G Ethernet will entail some unique considerations, as design margins will be extremely tight, making it mission-critical to optimize individual analog blocks to reduce impairments. Cadence's Rick Sanborn finds that knowing how best to debug common partitioning-related issues and implicitly control them using common features ... » read more

Managing Voltage Variation
By Barry Pangrle - 07 Aug, 2023 - Comments: 0

Engineers make many tradeoffs when designing SoC’s to better meet design specifications. Power, Performance and Area (PPA) are the primary goals and all three impact the cost of the implementation. For example, higher power and performance can both require more expensive packaging for power and signal integrity as well as cooling. The larger the die area the fewer die per wafer which drives u... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Aug, 2023 - Comments: 0

Qualcomm, NXP, Infineon, Nordic, and Bosch are jointly investing in a new RISC-V company, to be formed in Germany, that will speed up RISC-V’s adoption in commercial products. The company will be “a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry,” according to a press release. The co... » read more

Startup Funding: July 2023
By Jesse Allen - 02 Aug, 2023 - Comments: 0

Investors pumped more than $2.8 billion into 123 companies July. It was a particularly strong month for photonics companies, with a photonic integrated circuit foundry raising more than $100 million. Startups this month also are using photonic technology in innovative ways. This includes an all-optical RISC processor, biomarker identification, faster fully homomorphic encryption, and more AI... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2023 - Comments: 0

Siemens' Katie Tormala points to the need for die attach thermal testing to ensure efficient removal of heat dissipation from power electronics components to prevent premature failure or thermal runaway. Synopsys's Dermott Lynch notes that over 30% of semiconductor failures are attributed to electrostatic discharge, with damage ranging from leakages and shorts to junction and metallization b... » read more

Week In Review: Design, Low Power
By SE Staff - 28 Jul, 2023 - Comments: 0

Arm is helping to address the ongoing talent shortage through its newly announced Semiconductor Education Alliance, with a long list of partners, including Arduino, Cadence, Cornell University, Semiconductor Research Corp., STMicroelectronics,Synopsys, Taiwan Semiconductor Research Institute, the All-India Council for Technical Education, and the University of Southampton. The Alliance... » read more

Are In-Person Conferences Sustainable?
By Brian Bailey - 27 Jul, 2023 - Comments: 2

DAC/Semicon are now over, and while I missed a large part of it due to a stomach bug, I increasingly have a stale taste in my mouth about in-person conferences in general. Let's split things up – an event such as DAC is both an academic conference and a trade show. It has been that way almost since its inception 60 years ago. There are many other conferences that are pure conferences, and the... » read more

A Packet-Based Architecture For Edge AI Inference
By Pat Donnelly - 27 Jul, 2023 - Comments: 0

Despite significant improvements in throughput, edge AI accelerators (Neural Processing Units, or NPUs) are still often underutilized. Inefficient management of weights and activations leads to fewer available cores utilized for multiply-accumulate (MAC) operations. Edge AI applications frequently need to run on small, low-power devices, limiting the area and power allocated for memory and comp... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

The Good And Bad Of Chip Design On Cloud
By Ann Mutschler - 27 Jul, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about how the shift toward chip design on cloud has sped up, whether the benefits of cloud are realized in chip design, and some of the most pressing challenges to chip design on cloud today, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Syst... » read more

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