Challenges Grow For Creating Smaller Bumps For Flip Chips

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture.

For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM’s C4 (controlled collapse chip connection), but it really came into widespread use in the 1990s.

Since then, bump technology has evolved to handle increasing power and signal connection density required by memory, high-performance computing, and mobile computing devices. Meeting that demand requires new interconnect technology that enables smaller bump pitches, which currently is in production.

Viewed over time, the roadmap for flip-chip interconnect progresses from lead-free bumps to copper pillars, and then to copper microbumps. Pitch sizes continue to shrink, which in turn has created manufacturing challenges for bumping and bonding.

Fig. 1: Flip-chip technology pitch ranges. Source: A. Meixner/Semiconductor Engineering

Fig. 2: Flip-chip components. Source: Wikipedia

“In the flip-chip arena­ — 250-micron pitch and below — it originally was tin-lead bumps, and one of the big moves was to lead-free. But when you start reaching 100 microns or below, you start seeing more of a copper pillar, though there’s an overlap as we see copper pillars up to 250 microns,” said Jeff Schaefer, senior process engineer at Promex Industries. “With the 250-micron pitch, we see 130-micron bump sizes or copper pillar diameters. Once we get around the 100 micron pitch, it’s 80-micron diameter. The smallest I’ve seen is a 62.5 micron pitch with a 40 micron pillar. I expect to start seeing 50-micron pitch soon.”

The basic flip-chip process begins after circuit fabrication, when metal pads are created on the die surface to connect to the I/Os. Next comes wafer bumping, where a solder ball is deposited on each pad. The wafer is then diced, and those dies are flipped and positioned so the solder balls align with the substrate pads. The solder balls are then melted/reflowed, typically using hot air, and a mounted die is underfilled with an electrically insulating adhesive, usually using capillary action. [1]

Fig. 3: Flip-chip manufacturing process. Source: Wikipedia

Moving to a copper pillar or microbump requires lithography to create these structures.

“Copper pillar is generally used below 130µm pitch, because instead of being a circular solder bump, the copper pillar is mostly a Cu post with solder on top,” said Doug Scott, senior vice president of wafer level packaging at Amkor Technology. “This allows for the copper pillar bumps to be placed closer together without risk of the solder connecting together during assembly reflow — generally, ~40 µm Cu + ~25 µm.”

There are variations on the theme, as well. “Microbump, which is a common term used where you have an interconnect between silicon-to-silicon, is slightly different because the CTE (coefficient of thermal expansion) is generally the same,” said Mark Gerber, senior director for engineering/technical marketing at ASE Group. “Some of the general design rules used for copper pillar are the same, but the flat surface topography and low stress joints allow for flexibility of the underfill being used. This can also drive the individual bump pitch. Today, a 35µm bump full-array pitch is possible, due to the routing considerations mentioned before, for the wafer-level or fab-level routing that is used.”

The Heterogeneous Integration Roadmap [2] describes all aspects of packaging, including die-to-substrate interconnects ranging from wire-bonds to through-silicon vias. With flip-chip packages die-to-substrate interconnects, substrate redistribution areas, and substrate-to-board interconnects all play a role in the manufacturing limits.

Fig. 4: Conceptual diagram of flip-chip packaging. Source: A. Meixner/Semiconductor Engineering

Chapter 8 of the Heterogeneous Integration Roadmap [3] documents the landscape of current and projected packaging technology pitches. The minimum pitch of each flip-chip interconnect technology is captured in Table 1 of subsection 8.7 (page 41).

The corresponding table for substrate interconnect (the part that connects package to board) is found in subsection 8.8 (page 43).

With each change in interconnect technology comes new processes and their limits, which drive innovation, yield management, and defect inspection.

Bumping technology limits
Bumping technology is measured by pitch, size, height, and electrical and mechanical properties. Thermal considerations vary depending upon the CTE mismatch of material. Warpage is a concern for larger die and wafers, which is exacerbated by back grinding of a wafer prior to die attach.

“There are a number of drivers for pitch limitations for each type of interconnect,” said ASE’s Gerber. “Starting with traditional solder bump flip chip interconnect, the pitch capability is determined by collapse height for underfill, capture pad pitch for trace routing, capture pad pitch for bump-to-bump short risk and several other pitch related sensitivities. The pre-mounted bump height has a defined height, but as IBM defined the C4 term — Controlled Collapse Chip Connection — the diameter of the solder bump and the capture pad size will determine the ‘collapse or final height’ of the interconnect. This is the main pitch-limiting factor for using solder bumps related to pitch.”

Bump height is determined by design, but also processing choices. 

“For standard plated solder bumps and copper pillar bumps, pre-assembly bump heights are generally around 70µm to 75 µm, with collapsed bump heights after assembly of ~50 µm to allow for x,y,z space for underfill flow between the bumps. Microbumps will have much lower bump heights and involve plating much less solder. Specifically, microbumps can be less than 10µm tall with reduced Cu and solder heights depending on pitch and end need,” said Amkor’s Scott. “Standard plated solder bumps are generally used on pitches ranging from 130µm to 250µm. Below 130µm, there is not enough x-y space between bumps when starting with a 70µm pre-assembly bump height.”

Creating copper pillars requires more processing steps than solder bumps.

“When we transitioned to the die-to-die world the technology is different because now you’re dealing with a wafer and the planerites are so good compared to die to substrate. First you create the copper pillar, on the initial wafer that’s going to get the solder or the copper pillar there is first an under bump metal (UBM). It’s a little cap over the opening that goes down into the silicon. Then we build a copper core from that and then put a tin cap on it. So then the receiving wafer, they look like they have a UBM pad there and it’s usually has some nickel gold type plating on it so that it’s nice and pristine,” explained Promex Industries’ Schaefer. So instead of having a slight indentation like a laminate substrate, you have a slight extrusion. We’ve found that we’re able to actually solder them wet without ‘solder on pad.’ It’s how they’re designed and built. It almost acts like a solder and pad because it’s a little dome as opposed to trying to get down inside of a hole.”

“For copper pillar, which consists of a copper post and a solder cap at the tip, the copper post height can be defined to the limitation of one or more photo-resist layer thicknesses and as you reduce the pitch, the aspect ratio of the cu post height to pitch becomes the limitation along with the photo resist material and imaging tool capabilities,” said Gerber. “A secondary limitation for the copper pillar interconnect is the substrate design rules used. For fine pitch >110um pitch, 2 primary methods are used- BOT (Bond on Trace) or ET – Embedded Trace, where the solder cap of the copper pillar is placed on top of the trace instead of a traditional capture pad. Copper pillar size and shape, including the limitations above, can provide a limit to the capabilities and roadmap for continuing to shrink the pitches. Many of these limitations are due to the ability to route traces in-between the pillars on the substrate side. As new technologies are available, such as wafer-level RDL, the interconnect roadmaps will be pushed further, but still with limitations around the height/aspect ratio for manufacturing processes such as underfill.”

Others agree that underfill process comes with challenges. “As you get finer pitch smaller bumps, they get shorter. It’s now getting hard to find underfills to get underneath. The underfills have historically been designed to get under a 5-mil gap, and now they come down to 3 mils, which is 75 microns,” said Schaefer. “Now we’re starting to see 60 and 25 micron gaps. I’m sure people are working on new underfills. But there’s a lot of things to work on. For one, as you get finer particulates, it becomes more like a sludge, which makes it harder to flow. This is a roadblock that needs to be removed.”

Managing yield
As bumping technology gets smaller, additional processing steps — for example, lithography for creating copper pillars — open up new opportunities for yield detectors. For a successful bonding process, particulates, surface contaminants, and solder bump voiding are problematic for yield. These require process controls, metrology, and inspection.

Naturally controlling contamination is required. “Tier 1 OSATs invest to reduce the level of factory contamination sources, and therefore reduce defectivity percentages,” said Amkor’s Scott. “Pitch does not contribute to defectivity. Similar levels of defectivity exist regardless of pitch.”

But pitch adds some of its own challenges. “As pitch becomes smaller and the bump size is reduced, particle contamination management is very important. For other types of interconnects such as hybrid bonding, where pitches are reduced below 30µm and the surface-to-surface contact is important, wafer-based clean room environment is critical to yields,” said ASE’s Gerber.

Preparing for the underfill process should not be underestimated either.

“Generally with a laminate, you’re going to do an underfill after you do the flip chip,” said Promex’s Schaefer. “We determine where we will place it and how to reflow it. We clean it to get out any flux material under the gap between the die and substrate. Then we’ll underfill with an epoxy that flows. It’s designed to wet in and not leave voids and things of that nature. But there is a challenge as we get to finer pitches. Bumps get a little shorter, and as they get shorter the gap between the chip and the substrate gets smaller, so it’s harder to clean. Imagine sticking two glass slides together to try and get the dirt out between them.”

Metrology and inspection needs
For managing process control and yield, metrology and inspection tools play an important role. “There are tools available in the market that can help provide guidance on interconnect integrity, in addition to in-process cross-sectional analysis used at setup and at defined production intervals,” said ASE’s Gerber.

The bumping process and the bonding processes each have specific characteristics that need to be monitored. For bumps, metrology focuses on diameter, height, and co-planarity. Smaller pitches require more stringent control of bump diameter and height control. Similarly, as bump height shrinks, the window of co-planarity becomes smaller. Typically, 10% variation is allowed. For example, a 30µm bump height results in a permissible variation of ±3µm. Exceeding this contributes to unsuccessful or poor bonding.

Photolithography steps needed for Cu pillar formation comes with limits as well as the substrate design rules.

“Bonding is usually done with mass-reflow ovens,” said Mike Kelly vice president of advanced package and technology integration at Amkor. “The initial characterization of the reflow process is established using shadow-moire for quantifying the warpage during reflow, and temperature mapping of the ovens to ensure consistent temperature control of the flip-chip part itself. During setup, mechanical die lift and inspection to ensure good solder wetting is done. Also, flux is usually applied with a ‘dip flux,’ wherein the die bumps are ‘dunked’ into thin, tightly controlled flux reservoirs. Visual inspection of these items is done on a sampling basis.”

A variety of inspection and metrology tools are available to support package manufacturing.

Increasing automation of visual inspection reduces the reliance on operators to view an image and make a decision. The exponential increase in the bump connections is one driver. Changes to bonding processes provide another. A self-aligned solder reflow process is a mature technology. With the thermal compression bonding commonly used in advanced packaging, there are reliability mechanisms that pass electrical testing. That, in turn, prompts the use of X-ray inspection and metrology tools to view the bumps after bonding.

“For low-complexity packaging, manufacturers could get away with manual X-ray inspection by an operator. While feasible for parts with 100 bumps, scaling beyond 1,000 bumps is a challenge and requires new methods,” noted Frank Chen, director of applications and product management at Bruker. “As complexity increases, achieving sufficient quality and reliability requires investments in both process and metrology tools. Bump height variation is an important indicator of bonding quality. Upgrading to an automated in-line X-ray inspection that can monitor this metric for 100% of the products provides invaluable feedback for process control.”

Fig. 5: Bump height monitor from automated in-line X-ray inspection shows high correlation to bonding quality (validated by physical cross-section). Source: Bruker

“There are several methods that can or should be used to achieve process control. First, traditional 2D inspection (AOI) for 100% surface defect inspection per process flow (i.e., IQC, OQA, photo, clean, plating, etc.),” said Nathan Peng, product marketing manager at Onto Innovation. “Next, 2D metrology (AOI) can be used to control bump size and diameter sizing control. Furthermore, 3D metrology (AOI) can be used for a sampling bump height/co-planarity metrology information acquisition (this is typically done with a laser triangulation-based technology). Further, 3D metrology can target individual bump height characteristics, typically collected with white light interferometer technology. Also, there are methods to enable detection of organic residues on the bump top that can lead to failure with bump to pad connection.”

Conclusion
Products that demand higher interconnect counts continue to drive the interconnect roadmap. Each flip-chip technology has manufacturing limits that involve material properties, shrinking sizes that challenge underfill technologies, and increased use of lithography to create the interconnect structures. Any change in bonding processes results in an increase in metrology and inspection steps to meet yield and quality objectives.

References

1. https://en.wikipedia.org/wiki/Flip_chip
2. https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2021-edition.html
3. HIR Chapter 8 Single Chip and Multi Chip Integration, https://eps.ieee.org/images/files/HIR_2021/ch08_smcfinal.pdf

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