Closing The Test And Metrology Gap In 3D-IC Packages

The industry is investing in more precise and productive inspection and testing to enable advanced packages and eventually, 3D ICs.

The next generations of aerospace, automotive, smartphone, and wearable tech most likely will be powered by multiple layers of intricately connected silicon, a stark departure from the planar landscapes of traditional integrated circuits.

These 3D-ICs, composed of multiple semiconductor layers stacked and interconnected, offer groundbreaking advantages, and the industry is rapidly advancing toward 3D advanced packaging technologies to accommodate these new structures. But they also raise new challenges, not all of which have solutions today.

“3D packaging technology isn’t emerging anymore,” says Mark Kahwati, product marketing director for semiconductor testing group at Teradyne. “It’s happening. There is still going to be a lot of evolution with 3D packaging, because it’s not ready for prime time yet. The economics don’t make sense. But it’s really right in front of us.”

While 3D packaging offers significant benefits, it also introduces complex challenges in measurement and test verification. Companies now must develop precise, reliable tools to ensure the integrity of these sophisticated 3D structures and close the gap between test and measurement solutions being used for packages today, and what will meet the specifications required for the next-generation of packages.

“One of the big challenges is first identifying that there is a gap,” says Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology. “Helping customers see the metrology inflection points is a big challenge because maybe their internal roadmap hasn’t reached high enough complexity or because they are serving industries with lower reliability requirements.”

The precise evaluation of each layer, connection, and component within these compact 3D stacks is critical for ensuring the final products meet the rigorous criteria for quality and reliability required in data centers, and for automotive, aerospace, and medical applications. As device geometries continue to shrink and packaging becomes increasingly intricate (see figure 1), metrology must evolve in tandem to provide device manufacturers with detailed insights into the quality and potential defects of these multi-dimensional assemblies.

With the increasing complexity and smaller geometries in 3D packaging, maintaining consistent process parameters is critical, but it also can be challenging.

Fig. 1: Packaging configuration options increase to accommodate more I/Os. Source: Bruker

3D packages
The term ‘3D’ is often overused in the industry and can mean multiple things, depending on the user and context. It can refer to anything from a DRAM stack connected by wire bonds to a stacked architecture incorporating through-silicon vias (TSVs) and hybrid bonds.

“Packaging itself is evolving,” says George Orji, research scientist for the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). “It is no longer about packaging chips. Rather, it is about interconnecting chips and system integration, and that is really what is happening.”

As advanced chips proliferate, design teams are utilizing passive interposers and more complex active interposers with additional circuitry capable of integrating power or memory. Those complicate the definition of what 3D advanced packaging means. Despite the evolving narrative of what constitutes 3D, a key barrier to its widespread adoption continues to be the challenges of testing and measuring these complex packages.

“There are two things happening in parallel that are really challenging for 3D packaging,” says Brad Perkins, product line director at Nordson Test & Inspection. “It’s not just 3D that’s happening. It’s smaller pitch sizes and smaller interconnects. When you look at the physics behind penetrating into a package and identifying different layers in that package, there’s a lot more noise, or a lot more layers that you have to go through. For an older-style design, where you just had a CPU on a ceramic substrate, it’s pretty easy to see all those interconnects, and not that hard when you mount a layer below that. Now, when you start talking about three or four different layers worth of interconnects, or eight in high-bandwidth memory, how to penetrate down into those and not lose all your signals as you’re looking for smaller defects is really a challenge. We’re bumping up against the limits of physics and trying to figure those out.”

Test and metrology challenges for 3D packaging
A significant hurdle facing 3D packaging is the requirement for non-destructive inline methods that can accommodate the increasingly intricate designs featured in these devices. In addition, acquiring precise measurements within the complex stacks of a 3D-IC demands innovative approaches that surpass the current capabilities of traditional metrology. The difficulty increases exponentially when considering the process control needed for 3D interconnect structures, which are as much a part of the 3D packaging equation as the semiconductor dies themselves.

“Right now, there is a lot of talk about UCIe (Universal Chiplet Interconnect Express), and this comes with its own set of challenges,” says Teradyne’s Kahwati. “One is the ESD protection on those inner interconnects is weak to non-existent. How do you interact with that device without injecting a defect or causing latent defects? Another challenge is that the drive strength of those interconnects is pretty limited because it’s really meant for die-to-die. So a lot of the innovation we’re doing is on the tester electronics. How we can safely interact with these low-drive-strength interfaces and get the test quality that’s needed.”

As the device dimensions shrink, precise control over manufacturing processes like bonded wafer overlay becomes a critical factor in next-generation 3D-IC packaging. Solutions do exist, but the miniaturization trend underscores the need for even more refined test and metrology techniques — ones that can guarantee device parameters such as threshold voltage and leakage current are within required specifications.

“A significant test challenge is losing observability as dies are stacked,” Kahwati adds. “Test access vanishes, which is why there’s substantial effort in improving design-for-test (DFT) methods. These methods must evolve to maintain diagnostic stability and robust test strategies in the face of inherently obscured internal structures.”

Test and metrology become tremendously complicated when moving from the planar 2D topography to the volumetric 3D structures. Misalignments by even fractions of a micron can disrupt connections and degrade performance, leading to costly chip failures. In 3D configurations housing multiple dies, this can be very costly.

Fig. 2: As RDL layers increase at advanced nodes, measuring overlay shift and total overlay grows more complex. Source: Onto Innovation

The yield impact of packaging errors could be anywhere from 0.5% to 1.5%, said Bruker’s Chen. “There can be discrepancies between the electrical test results and metrology results. Even though it’s a small percentage, it’s important to perform enough metrology to identify marginal chips. If the defect is found later down the line, when the chip is integrated with more components, it gets much more expensive. Investing in metrology to prevent marginal chips escaping screening costs orders of magnitude less than failures in the field.”

Fig. 3: The cost of chip failure escalates as it proceeds to the board and system level. Source: Bruker

3D packaging standards
3D packaging also restructures the supply chain. “With 3D packaging and chiplets, you’re no longer tracking a simple one-to-one relationship between front-end parts and back-end components,” said Dieter Rathei, CEO of DR Yield. “Instead, you’re dealing with a web of relationships, multiple components condensed into a single device. Such complexity necessitates sophisticated tracking and metrology to ensure each part meets stringent quality standards.”

However, not all of the pieces are fully aligned or standardized yet. “So many things in 3D packaging are in development simultaneously across the industry,” says Keith Best, director of product marketing for lithography at Onto Innovation. “And the biggest issue is the actual chips themselves have no communications standards. Companies are not necessarily communicating with each other yet.”

There are many other issues still to be resolved, as well. The superimposed layers within a 3D-IC structure limit the visibility and accessibility of embedded features, making it challenging for test and metrology tools to focus on and measure specific points of interest within the stack.

Moreover, metrology in 3D packaging must account for the physical properties of the diverse materials involved, such as different thermal expansion coefficients (TCEs) across silicon, glass, and various interconnects. This is crucial as discrepancies in these properties can lead to thermal stresses and potential mechanical failures. Tools like laser flash analysis are employed to measure thermal diffusivity, a component in calculating thermal conductivity. And all of this requires more power.

“Power consumption keeps going up and up and up,” says Kahwati. “Under test, that sometimes is the highest thermal stress a device will ever see because you do scan patterns that aren’t representative of real workload. The benefit of approaching that thermal balance is you can optimize throughput for test and minimize test cost, but you don’t want to get so far over the line that you’re introducing stress or latent defects. That’s something we’re pushing the boundaries on now with the 3D-ICs, because the thermal limits keep growing.”

The stakes for precision measurements are at an all-time high. The success of 3D-ICs critically depends on the accuracy of each measurement and alignment throughout the fabrication process. Moreover, that precision is not just about the correctness of individual layers. It also includes the harmony of the entire stack. Each level must be flawlessly executed and aligned in reference to its partners, maintaining rigorously tight tolerances.

“People will probably find a workaround, such as how the bumping looks, or how the die-to-die bonding looks, or doing a lot of metrology on the connections,” says Marc Jacobs, product management advisor at PDF Solutions. “Because you can’t inspect through the silicon.”

Known good die
The industry’s presumptive solution for improving yield and quality of 3D devices is known good die (KGD). There are challenges implementing this concept, however, not least of which are inconsistent standards for what known good die means.

“There’s a significant industry challenge with what is really considered a known good die,” says Kahwati. “It’s an abstract term rather than a standardized definition. For instance, an OSAT may receive dies from a foundry that are deemed as ‘known good’ based on the foundry’s testing, but upon functional testing they fail to operate as expected.”

This suggests that a universal standard and traceability for known good dies are becoming increasingly important, shifting to a need for evidence and validation of what constitutes ‘known good’, including the test results and potential coverage gaps.

“There will be a dedicated effort to make known good die truly verified as such,” says PDF’s Jacobs. “Especially in areas where performance and power consumption are pivotal, such as chiplets, there is a necessary level of matching akin to ensuring the synchronicity between left and right channels on a stereo — but with a lot more complexity.”

Implementing KGD policies is a matter of component validation as well as a requirement for enhancing the functionality and reliability of a multi-chip system.

“Even though each individual chip may pass reliability standards, with multiple chip integration, one multiplies the probabilities of defects,” says Chen. “And the end result of creating a fully functioning and reliable device becomes more challenging even though the individual die quality didn’t change.”

Shared data analysis is key for determining known good die. The most critical applications require chips to be thoroughly tested under extreme conditions, often multiple times. A common assumption is that such thorough testing of those parts can provide insight into potential device failures in parts used for general consumer applications, but the opposite may offer better outcomes.

“My experiences go the other direction,” says Jacobs. “High-volume applications will actually yield benefits for the low-volume, super-expensive ones. Hard disk drive and video game consoles are both really high-volume applications, and they are relentless on quality. They have extremely good statistics. If you run a million units a day, how many defects you get per million is a knowable number and not a statistical calculation with a bunch of uncertainty.”

Still, ensuring quality in 3D-ICs is a challenge, considering the limitations of current test and metrology technologies for these advanced packages. The solution for finding all possible failures is more testing, whether at wafer probe, packaging, or functional testing. But increased testing also means slower throughput, lower yields, and increased costs.

“The cost of defects is not just the material scrap costs,” says Chen. “Some fab managers only think in terms of material cost and yield and how many parts they have to scrap as their cost of defects. They don’t consider how much it costs their customer if marginal chips are shipped and fail later in the field.”

And those costs can multiply with stacked die. “The scrap costs accumulate differently with 3D-ICs compared to monolithic devices,” says Kahwati. “With monolithic devices, you have the die cost and the packaging cost. But with 3D-ICs, costs literally accumulate geometrically. So it’s critically important to have known good die, and everybody wants known good die, but what that means from test is really enhancing coverage.”

High-reliability applications like aerospace demand such extensive testing to protect against failures, but consumer electronics may not require such measures due to their shorter expected usage span and lower associated costs of failure.

“What we often see in advanced packages are different requirements based on the application,” says Nordson’s Perkins. “You might have a conformal coating on a GeoPackage, which is something that same product would not have it if it’s going into a consumer device because you’re not going to worry about dendrite growth or other things that are going to happen over a short time period. If a personal computer dies after three years, nobody is that affected by it. If a satellite goes down after three years, people get a little upset about their $100 million investment.”

Emerging technologies
New test and metrology technologies are indispensable for 3D advanced packaging, especially those compatible with non-conventional substrates like glass. Techniques like 3D X-ray microscopy allow non-destructive examination of internal structures, offering a vital glimpse into layer alignments and interconnect integrity. Simultaneously, through-silicon-via technology bridges layers, a boon for electrical connectivity that nonetheless complicates inspection due to the obscured locale of these connectors.

A creative shift to scanning capacitance microscopy, with its promise to inform on sub-surface electrical properties, symbolizes the industry’s ingenuity in bypassing the depth-penetration limitations of traditional atomic force microscopy. Such advanced test and metrology techniques are not just supplementary. They are rapidly becoming crucial for ensuring the functionality and reliability of increasingly dense and high-aspect-ratio devices.

“Advanced packaging is a dynamic space right now. There are a lot of challenges,” says Nordson’s Perkins. “It’s a little bit early in the technology to really see how best to overcome some of those challenges, but where we’re really trying to do that is with tools that can help identify process drift in these complex packages.”

Processes like focused ion beam microscopy, 3D atomic force microscopy, and scatterometry offer high-resolution 3D imaging to examine intricate layer structures and analyze buried features inherent to 3D ICs.

“Customers are worried about marginal defects that electrical tests cannot catch, like partial non-wetting and voids,” says Chen. “Resistance testing might help identify some of these, but it takes long and sophisticated test patterns to catch them. Customers can also run more and more thorough electrical tests to catch some of the performance deviations, but then it’s just getting more expensive. They can’t afford to do 100% of that type of electrical test.”

Solving these challenges for 3D packaging will require metrology techniques capable of depth penetration and high-resolution 3D imaging. Tools such as focused ion beam (FIB) microscopy and 3D atomic force microscopy (3D AFM) enable detailed cross-sectional examination of layered structures. In the non-destructive regime, scatterometry leverages the principles of light scattering, and it provides another avenue to assess the buried features of 3D-ICs, although it must be adapted precisely for the nuances of vertical integration.

“Every single thing that you build for advanced packaging is different based on the architectures involved,” says Onto’s Best. “And, in fact, it changes once every quarter to six months.”

Addressing the data deluge
The innovation in test and metrology techniques to tackle the challenges of 3D packaging is accompanied by an explosion of data. The information gathered from each layer and each step in the fabrication process can be overwhelming. Sifting through this deluge to find meaningful insights — a practice often referred to as ‘big data metrology’ — requires intelligent algorithms and substantial computational power.

“The deployment of the model is tricky,” says PDF’s Jacobs. “You can take all the data from your production and do the math, and then run that in assembly and test. But your wafers may be coming out of a fab in Taiwan, getting sorted in an OSAT, then getting assembled in a different OSAT, and then getting final tested maybe in another OSAT. You understand in your head where all the data needs to flow, and you need to get that data to the right place at the right time, but actually getting the data to flow from one place to another is non-trivial.”

This abundance of data must be handled with cutting-edge data analytics and machine learning methods to rapidly identify trends and predict potential issues before they propagate through the manufacturing process.

“Managing the control of that data is a concern when two chips in a 3D package come from different companies,” says DR Yields’ Rathei. “We already have the problem in the fabless foundry model that foundries don’t have access to the test data, and the customer does not have access to equipment history to understand the production process.”

Beyond the hardware, metrology software has become a linchpin for 3D analysis. The complex interaction between layers in a 3D-IC stack requires robust modeling and simulation to predict and optimize outcomes. Emerging computational metrology methods, harnessing artificial intelligence and machine learning, promise to enhance the accuracy of measurements and expedite the identification of potential defects, thereby improving yield rates and reducing the cost of production.

“There’s a lot of work happening in data analytics,” adds Kahwati. “What can you do with that data beyond pass/fail or parametric results to give some indication about both the process as well as the device itself? There’s a lot of work going on there to really harness that data, and that’s still evolving, but it’s moving quickly.”

Conclusion
Test and metrology provide the foundation for comprehensive thermal management strategies in 3D-ICs. By integrating accurate measurement data into the design and monitoring processes, engineers can ensure that thermal issues are addressed proactively and maintain the reliability and performance of 3D-ICs across various domains — especially as such new materials as glass panels enter the fray. The continued evolution of metrological techniques will be a cornerstone in overcoming thermal challenges and realizing the full potential of 3D-ICs.