Unusual effects at 5/3nm, including fewer defects with double patterning.
Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography.
Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the performance in chips.
Used for chip production in fabs, EUV lithography makes use of a giant scanner that patterns tiny features in chips at advanced nodes. In operation, the EUV scanner generates photons, which eventually interact with a light-sensitive photoresist material on a wafer. This process is supposed to pattern precise features in chips.
That doesn’t always happen, however. In EUV, photons hit the resist, causing a reaction. The process is repeated several times. At each event, there might be a new and different reaction, due to the unpredictable and random nature of these processes. Thus, EUV is prone to what’s called stochastics, which describes events that have random variables. These variations, called stochastic effects, sometimes cause unwanted defects and pattern roughness in chips. Both can impact the performance of a chip or even cause a device to fail.
These issues were largely ignored in traditional optical lithography in years past. But with EUV, stochastic effects became a major concern, and they have become more problematic at each node. The good news is that the industry has found ways to mitigate the problem by improving the resists and processes. But stochastic-induced defects can crop up, creating headaches for foundry vendors and their customers alike.
“It means that stochastics are never going away as an important problem,” said Chris Mack, CTO of Fractilia. “Sometime around the 10nm or 7nm nodes, stochastic variations became the dominant source of variations in patterning. That’s mainly because all the other sources of variation kept getting smaller. Stochastic variations didn’t — or at least it didn’t shrink as much or as fast. It’s becoming a larger percentage of the total budget that we allow for variations.”
So it’s imperative to understand these effects, and it is equally important to locate stochastic-induced defects in chips in the fab. Fortunately, in recent times, several companies developed various tools that locate and even predict these defects in chips in today’s EUV processes. Going forward, though, the challenges escalate at 5nm and beyond. In response, several vendors are rolling out new and improved ways to find these defects, including:
Nagging stochastics
Chips are manufactured in fabs using a multitude of process steps, and lithography has been one of the most complex. For years, chipmakers used optical-based 193nm wavelength lithography systems to pattern the features on chips, but by the time they got to the 5nm node, it was too difficult to use multiple patterning.
EUV simplified the process, enabling chipmakers to pattern the most difficult features at 7nm and beyond. “When you go to EUV, you have a fewer number of masks. This is because EUV brings the industry back to single patterning. 193nm immersion with multiple patterning requires more masks at advanced nodes. With EUV, you have fewer masks, but mask costs for each EUV layer is more expensive,” said Aki Fujimura, chief executive of D2S.
Fig. 1: A typical sequence of lithographic processing steps. Source: Chris Mack/Fractilia
Samsung and TSMC inserted EUV lithography at the 7nm node in 2018. Now, both vendors are processing chips using EUV at 5nm. Others are developing EUV for chip production.
Chipmakers are in production using ASML’s EUV scanners. Incorporating a 0.33 numerical aperture lens with a 13.5nm wavelength, the system has 13nm resolutions with a throughput from 135 to 145 wafers per hour. ASML plans to ship 40 EUV systems in 2021 and 55 more units in 2022.
At advanced nodes, meanwhile, chipmakers face several challenges. An advanced logic process could have anywhere from 600 to 1,000 steps or more in the fab. At each step, a problem might occur, causing defects in chips. Therefore, chipmakers require inspection and metrology equipment in the fab. Inspection systems find defects on wafers, while metrology tools measure structures.
It’s a complex process. For example, atomic force microscopy (AFM) is one metrology tool type used in fabs. “With AFM, we’re inspecting nominally about a 50µm area over different chips and dies throughout the wafer. One of the key applications is looking at top-line roughness — being able to correlate line breaks and defectivity in those prints with subsequent defectivity,” said Sean Hand, senior staff applications scientist at Bruker.
Defects can crop up in other places. In operation, an EUV scanner is supposed to create various patterns in chips, such as tiny contact holes, lines, and vias, with good uniformity. But at times, the scanner may fail to pattern a required line, called a line break. The scanner can sometimes fail to print one or more of the contact holes, called a missing contact. In other cases, the process causes one or more holes to merge, sometimes called “kissing contacts.”
Line breaks, missing contacts, and kissing contacts are considered stochastic-induced defects. Another stochastic effect is line-edge roughness (LER). LER is defined as a deviation of a feature edge from an ideal shape, and it’s problematic because it doesn’t scale with the feature size.
“As the critical dimensions of lines reduce in both ArFi and extreme ultraviolet lithography, the magnitude of the roughness measured from these lines can be a significant fraction of the pattern linewidth,” said Charlotte Cutler, a principle process engineer at TEL, in a paper. DuPont and Fractilia also contributed to the work.
Many blame the resists for stochastic-induced defects, but they aren’t the only problems. Nonetheless, all stochastic-induced defects are problematic. “For example, if we can’t make our features sufficiently smooth, then we’ll have too much leakage current in our transistors. And we’ll get poor performance,” Fractilia’s Mack said.
Fig. 2: Fractilia’s technology detects LER in chips (top). Missing contacts and line breaks (bottom). Source: Fractilia
Tracing stochastics
The root cause of stochastic-induced defects is traced back to the EUV process itself. This process starts with a laser unit under the fab. First, laser pulses are fired and are then funneled into the EUV scanner in the fab.
Meanwhile, in the scanner, a small unit drops tiny tin droplets at high speeds. The laser pulses hit the tiny tin droplets, creating photons. Photons bounce off several mirrors within the scanner. Then, photons reflect off the mask and then hit the resist on the wafer. Chemically amplified resists (CARs) and metal-oxide resists are two common types of EUV resists.
The resists help form the desired patterns on the chip, although it’s a complex process. “In lithography, a wafer is coated with a light-sensitive material called photoresist. Light is then streamed through a photomask (a pattern of transparent and opaque areas), exposing the photoresist in some places, but not in others. The exposed regions are then etched away, while covered areas remain protected (in the case of positive photoresist). The end result is a set of features whose size and density are determined by the original photoresist pattern, reproducing the device design onto a film on the wafer,” explained Richard Wise, vice president at Lam Research, in a blog.
“When a photon strikes the resist, it sets off a chain reaction that changes the structure of the material, making it more soluble so it can be washed away in a subsequent development step,” Wise said. “Part of the reaction cascade involves a chemical amplification of the initial photon, where the photon is first converted into several electrons, whereby several photoacid molecules are eventually generated per incident photon.”
To make matters even more complex, EUV photons have 14 times more energy per photon than those in 193nm lithography. But for the same dose, EUV has 14 times fewer photons.
To illustrate these issues, let’s say you have $20 in pennies, or 2,000 pennies. Then, you have $20 in quarters, or 80 quarters. So, with quarters, you have 25 times fewer coins, but each one has more value.
The same is true with photons. In a hypothetical illustration, the pennies represent 193nm photons, while quarters represent EUV photons. With pennies, you have more photons.
In a lithography process, the idea is to generate as many photons as possible. In theory, this ensures that you will pattern the desired features on the chip with fewer variations. “So, the larger the number of photons, the smaller the variation will be as a fraction of that average,” Fractilia’s Mack said. “And so, the smaller the number of photons, the more variation there is. That’s called photon shot noise.”
Basically, a 193nm lithography scanner generates more photons with less energy. In comparison, EUV generates fewer photons, meaning there is a greater statistical probability of variation in the process.
In another example, let’s say a chip has a multitude of tiny cubic areas. “Then, you see how many molecules of the light sensitive part of the photoresist are in that cube, and how many photons of light get absorbed in that cube,” Mack said.
Ideally, the photons would be evenly dispersed and absorbed in each cubic area. That doesn’t always happen. In a hypothetical example, 48 EUV photons might get absorbed in one cube. In the next cube, 36 photons get absorbed. That’s a stochastic variation.
Compounding the problem is the fact that feature sizes are smaller at each node. As a result, you have a smaller cubic area with a fewer number of photons at play. That translates into a higher probability of stochastics.
So how does this all play out in the fab? As stated, chipmakers inserted EUV at 7nm using a single patterning approach. In single patterning, you put the features on one mask and then print them on the wafer using a single lithographic exposure. Originally, chipmakers hoped to use EUV resists with a 20mJ/cm2 dose.
“Dose is the amount of energy (per unit area) that the photoresist is subjected to upon exposure by a lithographic exposure system,” Mack explained.
At a lower dose (20mJ/cm²), chipmakers can print fine features at high throughputs. But a lower dose also means fewer photons, and a higher probability of stochastics.
As a result, chipmakers use a higher dose at 7nm, roughly 40mJ/ cm2 and above, but there are some tradeoffs. A higher dose translates into more photons, but the throughput of the scanner takes a hit.
Meanwhile, at 7nm, EUV single patterning is used to print features with pitches starting at 38nm or 36nm. But single-patterning EUV reaches its limit at 32nm to 30nm pitches.
Beyond 30nm pitches, EUV double patterning is required, which falls under the 5nm and 3nm nodes. Double-patterning EUV involves splitting a chip pattern into two masks. Each one is then printed as a separate layer.
EUV double patterning is more expensive, because there are more steps in the process. On the other hand, you can print larger features with a higher dose, thereby reducing the stochastic effects.
“Stochastics are still an issue, but EUV double patterning relaxes some of those concerns,” Lam’s Wise said. “EUV double patterning, while more costly has the advantage of enabling EUV to operate at a more manageable pitch. For example, if you wanted to print a 30nm pitch line, you can do it with direct print. But then stochastics are a significant challenge because the most significant factor in stochastics is the CD or the size of the feature being printed. By printing larger, you essentially capture more photons in a given feature and stochastics are improved. So your tradeoff is between the cost of double patterning in EUV versus the improvement you might see in things like stochastics, for example.”
Measuring, predicting EUV defects
Today, chipmakers are ramping up 5nm, with 3nm and beyond in R&D. “In principle, stochastics are getting worse going to smaller pitches, and resolving them is more challenging,” said Kurt Ronse, director of the advanced lithography program at Imec.
On the other hand, the industry has improved the EUV resists and processes. “The improved understanding and material availability established in the time frame from 7nm over 5nm to 3nm means that the defect levels at 5nm and 3nm are going down, allowing the same yield,” Ronse said.
Still, it’s imperative to locate and predict stochastic-induced defects in chips. In the fab, there are several ways to locate these defects, including optical inspection, e-beam technologies, and electrical tests. There are also various software tools here.
For years, chipmakers have relied on two types of equipment — e-beam and optical inspection systems — to find defects in chips. Optical inspection systems are the workhorse tools in fabs. In operation, a wafer is inserted in an inspection system. A light source generates a bright light that illuminates the wafer. The light is collected and an image is digitized. The system takes an image of a die and compares it to a chip with no defects.
Optical inspection systems are not only used to find common physical defects, but they are also used to locate EUV stochastics-induced defects. Optical has several advantages over other technologies.
“Stochastic-induced defectivity has improved significantly with production implementation and resist capability, however, it does still occur. Stochastic-induced defects are typically random by their very nature and can happen irrespective of pattern type,” said Andrew Cross, director of process control solutions at KLA. “We see that both conventional CD and newer hotspot e-beam metrology cannot flag these defects alone in such low defect density regimes. This drives the need for large area and high coverage inspection with sensitivity to capture critical patterning defects — requirements supported by optical inspection systems, particularly broadband plasma optical inspection.”
Stochastics are random in nature, and tend to affect weak patterns with highest frequency. “Therefore, the need for effective process window discovery is essential,” Cross said. “Process window discovery enables the identification of structures that are weakest typically in focus and dose. Since a specific structure normally repeats thousands, or tens of thousands of times within a design, predicting which may fail either due to the design itself, mask, or other process interaction, across die or across wafer, again requires high-coverage optical inspection techniques. Stochastics often occur within the process window defined by systematics alone, and either e-beam or optical monitoring can provide an effective solution dependent on the level of stochastics and how they impact a particular design. During this discovery we can try to distinguish between stochastics and purely systematic defects. Systematics generally affect exactly the same point within a design structure, for example, a specific corner or line end. Stochastics affect weak structures with highest prevalence, but they do not affect exactly the same point within the designed structure. Accurate design-based binning can help enable differentiation between stochastics and systematics.”
In addition to inspection and empirical discovery of stochastics, simulation can be a key enabler in predicting stochastics. “Regarding prediction of stochastics by simulation, an effective and accurate model is the biggest challenge. Model-based prediction of stochastic defectivity on a full chip could be an effective strategy, depending on accuracy and speed. The challenge here is to retain the accuracy of a physics-based model with sufficient throughput to cover the device,” Cross said.
Optical has some tradeoffs. “Optical inspection has an advantage in that it can scan full wafers in a short time. In that way, the number of defects/ cm2 can be measured, and hence chipmakers can estimate the yield for their chips,” Imec’s Ronse said. “The resolution of optical inspection may not be good enough to catch the smallest defects. Finding line breaks is a challenge.”
Meanwhile, there are other ways to find stochastic-induced defects in chips, namely tools using electron-beam technology, such as CD-SEMs and massive CD metrology.
Several vendors have developed massive CD metrology tools. Basically, this tool is a souped-up e-beam inspection system with metrology capabilities. They enable users to find defects in a large field of view.
In e-beam inspection, a wafer is loaded into the system. The system sends out an electron beam, which interacts with electrons in the material being scanned. That sends back signals, which are mapped. E-beam inspection has better resolutions than optical, but it’s slow.
Tasmit, a supplier of fab equipment, is the latest company to develop a massive CD metrology system. Tasmit’s new tool is used to identify defects in an EUV process using three steps. First, the tool is set to the SEM mode. Then, it performs inspection and metrology functions to collect defectivity and CD data from a wafer. Finally, massive inspection and intra-field CD metrology steps are conducted.
Using a 16μm field of view inspection mode, the tool achieves throughputs of 2.6hr/mm2. “We have shown a highly linear correlation between mean CD and break type defectivity on 32nm line/space patterns. Additionally, defectivity was predicted down to 0.89 defects/mm2,” said Seulki Kang from Tasmit in a paper. Imec contributed to the work.
There are other approaches. In a recent paper, ASML described the development of a new physical stochastic edge placement error (SEPE) model. This works with its e-beam inspection tool to locate defects.
The SEPE model incorporates several factors affecting contour uncertainty, including optical signal profile, photon and photoacid chemical kinetics, resist profile, and process window.
Using this model, lithographic simulations are run across a full chip design. Then, a stochastic variation model is generated. “From the simulated SEPE, a failure probability is calculated for each critical cut-line location. The failure probability of each pattern group is defined as the multiplication of the population and the defect probability. The pattern failure probability is used to identify the top hotspots by ranking defect criticality,” said ChangAn Wang from ASML, in a recent paper. “Then the locations of the top hotspots are used to guide an inspection tool to find defects on a wafer and validate the failure probability prediction.”
For years, meanwhile, the critical-dimension scanning electron microscope (CD-SEM) has been the workhorse metrology tool in fabs. CD-SEMs are also used to measure LER in chips.
A CD-SEM, which works like an e-beam tool, are used in many applications. But for LER measurements, CD-SEMs are sometimes prone to errors that bias the results.
Recently, Fractilia introduced a software tool to overcome these issues in measuring LER. The tooI, called MetroLER, works in conjunction with CD-SEMs from various vendors.
Fractilia’s technology separates the CD-SEM errors caused by bias. Then, it predicts the impact of roughness using a technique called power spectral density (PSD). “The PSD is a mathematical technique to statistically characterize a rough edge,” Fractilia’s Mack explained.
Fractilia is now addressing another patterning challenge—contact holes. In a recent paper, Fractilia and Imec described the development of an automated approach for analyzing contact holes using MetroLER.
In a study, researchers analyzed holes with pitches ranging from 46nm to 56nm. “The goal of automating the decomposition steps has been realized using MetroLER, with consequent reduction in time spent and the possibility of mistakes,” said Joren Severi, a researcher from Imec.
Meanwhile, there is another solution to find stochastic defects—electrical tests. For this, you pattern contacts on a structure. Then, you electrically test the structure.
“These are regular in-line electrical tests. If some lines are broken or bridging, the resistance measured indicates that there are failures. A large area can be covered and the measurement is very fast,” Imec’s Ronse said.
Conclusion
EUV is important. It enables the industry to pattern devices at the next nodes. At times, though, there are mishaps with EUV. So it’s important to take preventive measures from the very beginning.
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