Integration Hurdles For Analog And RF In Next-Gen Packages

A rapid increase in wireless connectivity and more sensors, coupled with a shift away from monolithic SoCs toward heterogeneous integration, is driving up the amount of analog/RF content in systems and changing the dynamics within a package.

Since the early 2000s, the majority of chips used at the most advanced nodes were systems-on-chip (SoCs). All features had to fit into a single planar SoC, which was limited by the size of a reticle. To add more features required shrinking all components on the chip. But because analog/RF did not benefit from scaling, analog/RF IP typically was re-engineered to be mostly digital with some analog (big D, small A). Now, with the cost of scaling skyrocketing, and diminishing power, performance, and area/cost benefits of scaling at each new node, the chip industry increasingly is focused on advanced packaging and chiplets at the leading edge of design.

This, in turn, has opened the door once again for purely analog/RF functionality developed at the optimal process nodes for specific features. It also allows more features, in general. But for chipmakers to add all of those features into a fixed package size raises some familiar challenges. The biggest ones today involve ensuring that analog/RF circuits — which generally are more sensitive to various types of noise, electromagnetic interference, and heat than digital circuits — will function properly over their expected lifetimes inside heterogeneous devices, even as the behavior of those devices changes over time.

“Analog or RF functions are considered very sensitive circuits. When RF receivers are integrated with digital functions on the same chip, digital noise can overwhelm the RF signal, necessitating robust isolation techniques,” says Jian Yang, senior director of technical product management at Synopsys. “RF encompasses anything wireless, from smartphone radios operating in various frequency bands to satellite communication and IoT devices. Analog functions, on the other hand, serve as interfaces between the digital and physical worlds, facilitating high-speed data transfer and signal processing in devices.”

The amount of RF and analog content used in devices is growing, using analog as a front-end interface to collect data, while leveraging the speed of digital processing to organize that data and identify patterns. “The demand for internal RF/analog functions is at an all-time high and is expected to increase,” says Vineet Pancholi, senior director for test technology at Amkor.

Packaging industry shifts
Combining these two worlds has never been easy, however. The integration of RF (radio frequency) and analog functions within advanced packaging has necessitated several innovations and changes in packaging technology to address the unique challenges these functions present.

“The improvements in the IC packaging industry that offer improved isolation between the digital, analog, and RF domains with compartmental shielding is partly responsible for the growth,” Pancholi says.

Fan-out wafer-level packaging has proved to be particularly useful for integrating RF and analog because it offers a sufficient number of I/Os in a limited RF die area and low parasitics, particularly resistance and capacitance. By eliminating the need for an interposer and using direct copper interconnections, FOWLP reduces signal loss and enhances signal integrity. Additionally, FOWLP supports higher degrees of miniaturization and improved electrical performance.

“There are two trends — fully integrating RF/analog blocks into one SoC using FOWLP, and multiple die integration into one package using SiP modules or chiplets,” explains Brian Hwang, vice president, fellow and manager of Amkor Korea’s System Solution Group.

Systems in package (SiPs) take advantage of through-silicon vias (TSVs), another advancement supporting the integration of RF and analog functions, allowing vertical stacking of multiple dies. That reduces the interconnect length and minimizes signal delay and power consumption. This vertical integration is especially beneficial for RF applications where signal timing and integrity are important. TSVs provide low-inductance and low-resistance pathways, essential for high-frequency signal transmission.

Microbumps also play a crucial role in advanced packaging by providing necessary interface numbers and capacity within a limited die area. This technology is particularly important for creating chiplets that combine RF/analog dies with high-end digital and memory components. By allowing finer pitch interconnections, microbumps help maintain signal integrity and reduce the parasitics associated with larger bumps.

Advanced substrate materials have been developed to support the integration of RF and analog functions. Low-loss substrate materials, such as glass or advanced ceramics, help reduce signal attenuation and improve the performance of high-frequency RF signals. Composite substrates that combine different materials leverage their respective benefits — thermal conductivity, mechanical stability, and low dielectric loss — to enhance the overall performance of the package.

Heterogeneous integration approaches, such as SiP and chiplets, provide flexibility and efficiency in integrating multiple dies with different functionalities. SiP technology allows for the integration of RF, analog, digital, and memory functions into a single package using advanced interconnects and encapsulation techniques. Chiplets enable the integration of pre-fabricated functional blocks, facilitating the combination of RF and analog functions with advanced digital logic and memory technologies.

“Demand will be increasing because the RF/analog functions will be designed and manufactured using the low-end process node or already-proven IPs, but digital IPs and memory will be designed and manufactured using high-end processes and advanced technologies,” says Amkor’s Hwang. “So there will be a gap between RF/analog IPs’ demand and digital/memory IPs’ demand in one system.”

Testing challenges
Testing advancements are essential for managing the complexity and ensuring the quality of advanced semiconductor packages that integrate RF and analog functions. Advanced characterization and high-frequency testing techniques, such as network analyzers and time-domain reflectometry, can accurately characterize RF component performance. Additionally, built-in self-test (BiST) circuits for RF and analog functions allow real-time monitoring and diagnostics.

Fig. 1: RF analysis capabilities. Source: Synopsys

“Testing RF and analog elements in advanced packages like RF-SOI (radio frequency silicon-on-insulator) and 3D-IC requires a combination of specialized equipment, advanced simulation tools, and intricate knowledge of both semiconductor physics and the specific characteristics of each packaging technology,” says Jeff Cheng, director of testing and packaging support at UMC. “As the complexity of these packages increases, so does the complexity of the testing required to ensure device performance and reliability.”

For example, RF probe testing with microbump technology presents several challenges, primarily due to the small size and fine pitch of the microbumps. The tiny dimensions of microbumps make accurate probing difficult, as the probes must be precisely aligned to make reliable contact without damaging the delicate structures. Additionally, maintaining signal integrity during testing is challenging because the high-frequency signals can easily be distorted by even minor imperfections in the probe contact. The mechanical stress exerted by the probes also can lead to deformation or breakage of the microbumps, further complicating the testing process. To address these issues, advanced probe designs and materials, as well as meticulous calibration and alignment procedures, are necessary to ensure accurate and reliable RF testing of microbump-equipped devices.

“For analog, mixed-signal type of circuits, BIST goes into the design,” says Synopsys’ Yang. “For an RF type of integration, accessibility is still a challenge. Where do you place the probe? How do you design the probe board to ensure clean signal stimulus and minimal loss from the probing and test fixtures?”

Testing processes also face significant challenges when dealing with minimum pitch configurations on advanced packaging. The reduced spacing between interconnects increases the risk of short circuits and crosstalk, as even minor misalignments can cause adjacent lines to interfere with each other. Ensuring precise alignment is crucial, but it becomes increasingly difficult as the pitch decreases, requiring more advanced and accurate equipment. Additionally, the reduced pitch makes it harder to maintain signal integrity, as the close proximity of interconnects can lead to signal degradation and increased electromagnetic interference. These challenges necessitate the development of specialized tools and techniques to accurately handle, inspect, and test minimum pitch configurations without compromising the performance or reliability of the semiconductor devices.

“The overall data bandwidth is continuing to increase, and so is the RF bandwidth for over-the-air transmission,” says Amkor’s Pancholi. “To support this growth, the per lane data rate is increasing. With multiple in/multiple out (MIMO) and carrier aggregation methodologies, higher data rates are made possible. Multi-channel RF transceivers for cellular, Wi-Fi, Bluetooth, SATCOM, and automotive applications require custom RF signal path designs that are optimized for performance per the carrier’s frequency and bandwidth requirements within the package designs. Accurate and efficient RF production testing requires complementary test technologies like automatic test equipment, wafer probes, and package handlers, and most importantly, a carefully architected test hardware/probe card and loadboard and socket design.”

All of this needs to fit within the chip’s cost budget, as well. “The key challenges for testing RF/analog packages are in the production application development that optimizes production throughput at the lowest cost,” Pancholi says. “The tradeoffs include RF signal path, digital signal path, power and clock routing, maximum parallelism, package handling, and others. The considerations for each of these are unique for each RF band FR1 (sub-8GHz), FR2, FR3 (mmWave), ~60GHz, ~80GHz, and so on.”

3D-ICs will present other testing difficulties. The complexity of these structures can lead to signal integrity issues, including signal loss, delay, and cross-talk between layers. High-frequency testing and advanced modeling are necessary to predict and mitigate these issues.

“Given the layered nature of 3D-ICs, electrical testing must be conducted at various levels of integration,” says UMC’s Cheng. “This includes testing individual layers before they are bonded, and testing the entire assembly for voids, delamination, and other defects that could impair connectivity and device reliability. This multi-level testing complicates the test process and requires sophisticated test strategies and equipment.”

Isolation techniques within packages
Shielding and isolation techniques are essential for preventing interference and ensuring signal integrity in integrated RF and analog systems.

Advanced packaging now incorporates ground shielding around sensitive RF signal traces to prevent electromagnetic interference (EMI) from digital components. This involves surrounding sensitive RF signal traces with grounded conductive material, creating a shield that blocks external noise from digital components. The grounded shield acts as a barrier, absorbing and diverting stray electromagnetic signals away from the RF traces.

Where ground shielding provides a precise and targeted approach that helps mitigate the impact of nearby digital noise on individual RF traces, compartmental shielding creates physical barriers within the semiconductor package to isolate entire functional blocks or regions. These barriers, often made of metal walls or trenches, compartmentalize the RF, analog, and digital domains, preventing cross-talk and interference between them.

“The principal signal path isolation technique is to surround the signal trace with ground all around,” says Pancholi. “Compartmental shielding within the package, socket designs, and test fixtures all apply the same principles to isolate signals from aggressor or stray signals.”

Advanced simulation tools are indispensable in the design and optimization of isolation techniques within semiconductor packages. These tools enable engineers to model the electromagnetic interactions within the package, allowing them to predict and mitigate potential interference issues before manufacturing. By simulating various design scenarios, engineers can optimize the layout and shielding strategies to enhance isolation performance. Advanced simulation helps in fine-tuning the placement of ground shields, compartmental barriers, and other isolation techniques, ensuring that the integrated RF and analog functions perform reliably in real-world conditions.

“Co-design and simulation capabilities are essential to check isolation and shielding performance,” says Hwang. “Techniques such as trench isolation, wire shielding, and the use of metal chips are employed to enhance isolation within the package. These measures help mitigate the impact of digital noise on sensitive RF signals, ensuring reliable performance.

Other methods like trench and wire shielding are employed to provide additional isolation within semiconductor packages. Trench isolation involves creating deep trenches filled with insulating material to separate different functional areas. This method is particularly effective in preventing cross-talk and ensuring signal integrity by physically isolating sensitive components. Wire shielding, on the other hand, uses conductive wires to create an EMI shield around sensitive RF components. These wires act as a barrier, diverting electromagnetic interference away from the critical signal paths.

Thermal management
Thermal management is a significant challenge in mixed-signal IC packaging, particularly with high-power RF components such as power amplifiers and digital cores.

“A typical example is the RF power amplifier, which operates with an efficiency between 10% and 45%, meaning that over half of the power is dissipated as heat,” says Yang. “If the heat is not effectively removed, the device’s junction temperature can exceed safe limits, leading to malfunctions.”

Embedded cooling solutions, such as microfluidic channels, can actively manage the heat generated by high-power components. Dedicated heat spreaders and sinks within the package also help dissipate heat effectively, ensuring components operate within safe temperature ranges. But thermal issues remain problematic in 3D-ICs, where heat can become trapped between different metal layers. This is particularly true for heterogeneous designs, where proper placement of different logic and memory chiplets requires a deep understanding of how a chip will be used, including partitioning and prioritization of different logic and memory elements using real workload simulations.

“3D-ICs stack multiple layers of active electronic components, which can lead to significant thermal buildup,” says Cheng. “Testing must include thermal profiling to ensure that heat does not degrade performance or lead to reliability issues. Thermal management strategies may involve both passive and active cooling techniques.”

Others point to similar concerns. “Thermal management strategies should be simulated at the package level,” adds Hwang. “Materials like metal TIMs (thermal interface materials) can support better thermal performance.”

In addition to advanced TIMs and heat spreaders, innovative materials such as gallium nitride (GaN) are being used to improve performance and thermal management. “The thermal conductivity of GaN is significantly higher than that of silicon, making it a preferred material for high-power RF applications,” adds Yang “GaN can handle much higher power levels and offers better thermal performance, which is crucial for applications like 5G base stations and radar systems.”

Passive cooling solutions such as heat sinks and spreaders are essential for managing thermal loads in high-power RF components, as well. These components must be designed to maximize heat dissipation, maintaining the overall reliability and performance of the semiconductor device. Active cooling techniques, including the use of microfluidic channels, provide additional thermal management by actively transporting heat away from the hot spots.

Overall, addressing thermal challenges in advanced packaging involves a combination of materials innovation, precise thermal simulation, and the implementation of both passive and active cooling strategies. These measures are essential to maintain the performance and longevity of RF and analog components in increasingly complex and power-dense semiconductor environments.

Conclusion
The integration of RF and analog functions within advanced semiconductor packages is becoming essential for enhancing the performance of applications such as smartphones, IoT devices, radar systems, and 5G base stations. This integration drives the need for innovative packaging technologies like FOWLP and TSVs, which enhance performance by reducing signal loss and improving miniaturization. The shift toward heterogeneous integration, including SiPs and chiplets, provides flexibility and efficiency, allowing the combination of RF, analog, digital, and memory functions into a single package. However, testing these complex packages presents significant challenges that require sophisticated tools and methodologies to ensure accurate and efficient RF production testing.

Addressing the integration of RF and analog functions involves overcoming significant challenges in isolation, testing, and thermal management, with ongoing advancements in packaging technologies and materials being crucial to meet growing demands for high-performance, reliable semiconductor devices.

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