Metrology Strategies For 2nm Processes

Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the boundaries of existing tools.

Semiconductor metrology is all about characterizing, monitoring and controlling individual semiconductor processes to maximize the production of yielding devices. Metrology and inspection platforms walk a fine line between having the ability to measure the smallest defects or pattern marginalities, but over relatively large fields of view to ensure high yield across 300mm wafers.

To meet the needs of N3-generation devices with sub-20nm pitch, tools based on optical, electron beam (e-beam), X-ray, scanning probe (AFMs), and other systems must measure relevant parameters at speeds that keep pace with work in process (WIP). Measurement precision and accuracy are paramount. The goal of wafer inspection is to detect killer defects that impact yield, typically ranging from 10% to 30% of the size of critical features.

Fig. 1: Higher sampling rates and a broader array of measurements techniques are needed to control complex, 3D device structures from the transistor to packaged device level. Source: Nova

Metrology and inspection needs at critical nodes are increasingly impacted by the broad range of new structures in fabs (see figure 1). These include SiGe/Si stacks in 3D nanosheet transistors, fully depleted silicon on insulator (SOI) devices, new backside power delivery methods, and chip stacking technologies enabled by hybrid bonding.

The International Roadmap for Devices and Systems (IRDS) spells out this paradigm shift: “Broadly speaking, the shape, number, and location of parameters needed to characterize logic and memory device structures pose a greater challenge than size alone. Sub-20nm features are difficult to measure. However, device structure complexity and use of new materials further complicates a challenging environment.” The expanded array of critical metrology and inspection technologies starts with metrology that supports the patterning process.

EUV productivity
As the use of EUV lithography (EUVL) gains momentum, EUVL-induced stochastics have become a leading challenge. Stochastics refers to pattern variability that can cause defects in patterned resist films, and has emerged as a key metrology hurdle. Because CDs are typically measured using CD-SEMs, software that addresses stochastic variations is tied to CD-SEM output. Overlay, with its continually shrinking budget, remains a constraint in increasing device yield.

At their best, metrology systems are key enablers in manufacturing process development, control, and improvement, and faster yield ramps — often through better analytics incorporating AI methods. And because metrology platforms are developed years before they enter high-volume manufacturing in fabs, their development follows trends.

“Metrology of complex 3D structures has posed multiple challenges over the past few years — in 3D NAND and advanced logic, and now we also see indications of customers moving to 3D DRAM,” said Shay Wolfling, CTO of Nova. “And advanced packaging, by definition, is a complex 3D structure. We see more and more that advanced packaging challenges resemble those of the semiconductor front end, both in terms of customer interest but also in terms of dimensional and materials technology complexity.”

Key trends, therefore, revolve around:

• Device structures and new material complexity, which drive metrology needs as much as continued scaling;
• Hybrid metrology methods, which will prevail going forward because no single technique addresses all the parameters and measurements needed, and
• Faster measurements, which require brighter sources and more channels to provide more data for processing.

Ideally, metrology systems take advantage of smart data analytics with AI and deep learning tools to eventually address all aspects of metrology, including image and data analysis, inference, integration with modeling and simulation, predictions, and correlations with wafer process steps.

“Not only do you need to do the data acquisition at extremely high rates, but you also need to be able to process all that data and generate high-fidelity 3D maps,” said Tim Skunes, vice president of research and development of Nordson Test & Inspection’s CyberOptics Division. “So the competence of your algorithms needs to be very high.”

Optical’s strengths
The highest throughput systems, all optically based, are the tools of choice for integrated metrology (with the process chamber) and in-line (standalone) process control. At the same time, more 3D structures in NAND flash, advanced logic, and new 3D DRAM are giving rise to tools with multiple light sources and multiple detectors to resolve 3D structures while accelerating throughput.

Today, Onto Innovation, Nova, Applied Materials, KLA, and Hitachi High Tech offer multiple platforms with production-worthy throughput.

At the 5nm and 3nm nodes, chipmakers are transitioning from double or quadruple patterning using deep UV lithography (193nm), to EUV lithography (13.5nm) at critical levels (transistor definition, first metal layers) to pattern 25nm features. Compared to 193nm, EUV enhances lithography resolution while reducing the number of lithographic passes, improving fidelity and reducing manufacturing costs. The transition to high-NA EUV is expected to enable 20nm patterning with 13nm self-aligned double patterning.

Defects on masks
Proper control of the variation in transistor gate length starts with mask metrology.

“Masks and wafers are different in that the same mask is used to manufacture all the chips on all the wafers, so a defect on a mask is a defect on all wafers,” said Aki Fujimura, chairman and chief executive of D2S. “By and large, masks are repaired as much as possible.”

To help with patterned mask inspection, Lasertec introduced improved actinic mask inspection, which identifies printable mask defects. Actinic inspection uses a high-power EUV source (13.5nm) to produce high-resolution, high-contrast images of defects — most importantly, capturing phase defects that cannot be resolved using non-actinic deep UV inspection.[1] A combination of actinic patterned mask inspection (APMI) and multibeam e-beam inspectors from ASML can capture more of these mask defects with the higher throughput enabled by multibeam inspection.

Fujimura noted that curvilinear masks, which do a better job of producing ideal wafer patterns using EUV — also termed inverse lithography technology — are replacing Manhattan style mask layouts. “Curvilinear mask shapes as designed by ILT make metrology, inspection, and repair more involved. As real shapes on masks (vs. CAD drawings) have always been curvilinear, even for CAD shapes drawn as Manhattan shapes, there isn’t that much difference at the foundational level. But at the practical level, such as considering the efficiency of data representation of curvilinear shapes, the data flow and tools require maturity as the industry works on curvilinear formats as a SEMI standard.”

Metrology in the lithography cell
There are three metrology activities performed in the lithography cell – material and tool qualification, process window discovery, and process window qualification and control. Material and tool qualifications often use unpatterned wafer inspection tools to check for defects prior to production use.

During process window discovery, lithography engineers perform multiple design of experiments (DOEs) to quantify the process margin boundaries. Process window expansion involves purposely modulating the scanner’s exposure and dose values across a wafer, for instance, to identify hot spots, typically using DUV inspection. In addition, overlay — the lining up of one feature over an underlying feature — can be modulated to identify pattern sensitivities in the layout and further quantify the process window. These analysis are performed using a high-resolution optical inspection system followed by e-beam inspection to confirm actual defects. Atomic force microscope (AFM) measurements, a type of scanning probe, act as reference standard (CD-AFM).

Optical and e-beam systems each have their strengths and often work in tandem. For defect detection, optical systems do the best job of detecting random defects across the wafer, wafer-to-wafer, and lot-to-lot defectivity trends. E-beam inspection, whether it uses a single column or multiple beams, provides superior accuracy and sensitivity over optical methods, and is very good at detecting repeating (systematic) defects. Unfortunately, low throughput still limits the layer use in high volume manufacturing.

3D structures create stress and distortions that contribute to edge-placement errors. NAND flash chip makers were the first to incorporate widespread wafer shape metrology, which work in concert with overlay and other metrology tools to feedforward irregularities to the scanner, which compensates for local wafer shape from wafer center to edge. According to Applied Materials, fabs most often quantify the overall error, known as edge placement error, which incorporates CD, overlay, and process variation (see figure 2). The company also identified a trend away from single-layer patterning control at critical lithography steps to multilayer integrated control where process windows for two to three layers are statistically optimized together.

Optical systems have evolved to using a range of wavelengths (broadband UV inspection), using polarized light (ellipsometry), or using multiple angles of scatterometry to gather more information about devices. In addition to wavelength and polarization, the phase of the light can produce additional sensitivity to topography measurements.

Either image-based overlay measurements or scatterometry are used in high-volume production. With image-based targets in the scribe line, which are typically 5X larger than the device features, measurements are corrected for this metrology-to-device offset. CD-SEM captures the local variation including stochastics. Chipmakers are both moving to smaller targets and using in-field targets to better represent the actual device features. Moire effect targets — a superimposed network of lines that when imaged with scatterometry cause reflection differences that correspond with alignment shifts — are enabling customers to minimize total measurement uncertainty in overlay.

Fig. 2: Fabs are moving toward multilayer measurements that capture all the yield-limiting contributors to edge placement error. Source: Applied Materials

The ability to select appropriate wavelengths of light for the application is important. 3D NAND stacks, for example, typically are made up of silicon dioxide and silicon nitride layers, so the near infrared band ellipsometer works well.

“For 3D NAND stacks that can be tens of microns thick, we have a tool called the Aspect, that utilizes the mid-infrared wavelength of 5 to 10 microns,” said Nick Keller, director of application development at Onto Innovation. “We’re using that light for a couple reasons, because the stack is so thick, but also because you get these strong absorption bands from the dielectric materials. So the ellipsometer uses the absorption bands to filter different depths by wavelength. With modeling, you can basically get the entire profile of the structure.”

Following high aspect-ratio etching, the system provides in-line measurement of large arrays of, for instance, 80:1 aspect ratio channel holes in a single measurement. AI Diffract software helps process the data quickly.

Machine learning is playing an increasing role in metrology. “The big advantage of optical tools is that you can measure multiple parameters while covering large areas rapidly. The key issue is how do you correlate the sensitivity to the actual parameters of interest,” said Nova’s Wolfling. “We’ve shown that with good machine learning training, we can use optical metrology for applications that were previously used by slower AFM or CD-SEM. We take a CD-SEM or an AFM as a reference to train our optical measurement, and via this training we are able to detect and quantify, for example, line-edge roughness and topography variations optically.” He notes that CD-SEM and AFM will still be used to monitor and continuously improve the training of optical tools.

Nanosheet transistor metrology
Despite the general similarities with finFET architectures, nanosheets — or more generally gate-all-around transistors — feature hidden gaps between the nanosheets, which are challenging to inspect and measure.

Fig. 3: A combination of metrology techniques are needed to produce all the necessary measurements for 3D structures. Source: Nova

Strain-based structures can be characterized in-line using Raman spectroscopy, which complements other methods. “Raman spectroscopy is being used by a number of customers in high-volume production to monitor strain and stress and crystallinity in device structures. So Raman is very sensitive to monitoring the crystal phase of the device or detecting defects or residues around silicon-germanium,” said Wolfling.

He added that Raman spectroscopy actually performs better with direct on-device measurements than bulk material properties. “It’s very material-sensitive,” he said. “For instance, silicon germanium in finFET and silicon germanium in the bulk will not generate the same raw signal. This method is consistent with the general trend toward on-device measurements.”

BEOL metrology and inspection
Scatterometry is a diffraction-based metrology workhorse that plays a key role in trench depth, contact, and via structures, as well as complex 3D structures. Scatterometry provides line-shape metrology as well as average metrology values for a number of parameters using single wavelength or multiwavelength tools. It also can offer improved total measurement uncertainty over image-based metrology.

Nova developed its spectral interferometry method, which collects light phase information in addition to the intensity of the reflected beam. The advantage is higher sensitivity measurements, but also an ability to select the layer to measure without getting interference from underlying layers.

Hybrid bonding
The trend toward 2.5D and 3D packaging creates significant challenges for metrology and inspection tools. “On the issue of advanced packaging, hybrid bonding is a very powerful area and a significant inflection,” said Wolfling. “In such applications, planarization and polishing play a key role. When you bond wafers together, they need to be extremely uniform. We therefore see more and more CMP metrology requirements for both integrated metrology as well as standalone OCD solutions for these layers in bonding.”

Hybrid bonding is so called because it connects copper interconnects from one device to another and connects the dielectric fields in between. At about 10µm pad pitch, hybrid bonding is needed because thermo-compression bonding, which bonds microbumps to microbumps, no longer can be reliably extended.

In addition to optical tools, AFMs are being used extensively in R&D to develop the appropriate recessed copper profile needed prior to hybrid bonding. AFMs have the specific z-height resolution needed to precisely map the profile from one feature to another.

Overlay metrology for lining up two bonded wafers uses infrared microscopy (1310nm or broadband), which can penetrate the full depth of the silicon wafer. This metrology is necessarily built into the hybrid bonding tool.

Bonded interface defects and voids must be detected. Indeed, the need for defect-free bonding surfaces is part of what makes wafer-to-wafer and die-to-wafer bonding so challenging to move from R&D into production.

Scanning acoustic microscopy (SAM) using ultrasound waves through DI water can detect such voids, but concern over hermeticity is driving the development of dry or spray techniques to preserve the bonded wafer interface. Ideally, defect review procedures are developed for bonded wafers in HVM.

“There are still a lot of challenges with hybrid bonding, and maybe the biggest challenges are not so much technical, said Skunes. “It is the number of different parts of the ecosystem that have to come together to really kind of make it happen.”

Fig. 4: Defect review of failures showing 2D and 3D images. Source: CyberOptics Division, Nordson Test & Inspection

In wafer level packaging, bump metrology is important to ensuring thousands of bumps per wafer meet specifications. Skunes noted that the parameters of greatest interest for microbumps include XY offset, bump diameter, local bump height, and bump coplanarity per die. Optical review for solder pastes can measure the XY offset, area, volume and detect bridging. For instance, optical review results show the 2D and 3D images captured by the MRS sensor (see figure 4), and there is an additional high magnification optic with 0.2µm height resolution.

“We believe 100% inspection will be a game changer, particularly in market segments such as automotive, where the electronics content in a vehicle continues to grow at a rapid rate,” said Skunes. The company’s optical inspection tool uses up to four detectors to image wafer microbumps with a 5µm lateral resolution (x-y) and submicron z resolution.

Bruker’s Frank Chen, director of applications and product management, recently described failure analysis performed on failed in-field memory devices that contained latent defects. They passed probing and electrical stress testing during manufacturing, but when FA analysis was performed using defect review with x-ray CT (computed tomography), it revealed marginal defects on multiple bumps that were missed by the customer’s sampling strategy. “Part of the reason why the yield management strategy hadn’t shifted was due to the lack of in-line technologies that could capture these buried latent defects quickly and reliably,” he said.

Conclusion

Existing metrology methods are being extended to meet the needs of a growing list of 3D applications, while new technologies make the journey from lab to fab for specific applications. Solutions are being tailored to the materials measured but also the new architectural demands of 3D integration.

Reference
1. Tsunehito Kohyama, Hiroki Miyai, and Toshiyuki Todoroki “Actinic patterned mask inspection for EUV lithography”, Proc. SPIE 12325, Photomask Japan 2022: XXVIII Symposium on Photomask and Next-Generation Lithography Mask Technology, 123250H (15 September 2022); https://doi.org/10.1117/12.2642098