A new technical paper titled “A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity” was published by researchers at the Tokyo Institute of Technology.
Excerpt
“A new ultralow-voltage retention (ULVR) SRAM cell is proposed, which can highly enhance the noise margin (NM) for the ULVR mode at ultralow voltages (VUL). This 8T cell is configured with newtype Schmitt-trigger (ST) inverters that can nearly maximize the hysteresis width of the voltage transfer characteristics (VTC). The design methodology of the cell is developed with careful consideration for the process variation of the constituent transistors, and the optimally designed cell can ensure sufficient NMs that satisfy the 6σ failure probability for all the operating modes. In particular, for the ULVR mode at VUL = 0.2 V, the proposed 8T cell can exhibit much stronger noise immunity than previously proposed various lowvoltage cells. In addition, the proposed 8T cell can achieve stable data retention even at VUL = 0.16 V with sufficient noise immunity satisfying the 6σ failure probability. An 8kB ULVR-SRAM macro configured with the proposed-8T-cell array is also developed. Using the ULVR mode, the macro can reduce the standby power by ~93% compared with the standby mode of a conventional 6T-SRAM macro.”
Find the technical paper here. July 2025.
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