tag: 10nm

What If EUV Fails?
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

Gaps In Metrology Could Impact Yield
By Mark LaPedus - 17 Apr, 2014 - Comments: 0

For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more

Mask Hotspots Are Escaping The Mask Shop
By Various Writers - 16 Apr, 2014 - Comments: 0

Although the overwhelming majority of wafer production issues at the 28nm-and- below process nodes are lithography- and OPC-related, the semiconductor industry is starting to see problems caused by mask hotspots: wafer-level production issues that are caused when the shapes specified by optical proximity correction (OPC) are not faithfully reproduced on the mask. Mask hotspots will account for ... » read more

Power Moves Up To First Place
By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

Tech Talk: Multipatterning, Take Two
By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

Litho Is Out Of Sync
By Ed Sperling - 20 Mar, 2014 - Comments: 0

EUV’s repeated missed deadlines, and the slow-motion response by the rest of the industry to fill the void with alternatives, is having ripple effects in every facet and corner of the semiconductor industry. It’s making design harder and more expensive, introducing potential errors into the DFM flow, and greatly increasing the amount of time it takes to process wafers. It’s also adding a ... » read more

EUV Reaches A Crossroads
By Mark LaPedus - 20 Mar, 2014 - Comments: 3

[gettech id="31045" comment="EUV"] (EUV) [getkc id="80" comment="lithography"] is at a crossroads. 2014 represents a critical year for the technology. In fact, it may answer a pressing question about EUV: Does it work or not? It’s too early to make that determination right now, but there are more uncertainties than ever for the oft-delayed technology. Originally aimed for the 65nm node in... » read more

One-on-One: Naoya Hayashi
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the current and future challenges in the photomask industry with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). SE: What are the big challenges for the photomask industry today? Hayashi: There are several challenges. Most of the challenges involve mask complexity. It is also quite difficult to handle the mask data, because it is ... » read more

Advanced Lithography: Moore’s Law Moves On
By Marc David Levenson - 20 Mar, 2014 - Comments: 1

Every February, experts in nano patterning technologies converge in San Jose, Calif., to present their road maps, brainstorms and results at the SPIE Advanced Lithography Symposium. This year, there was more confusion than ever, partly the result of sessions in unlabeled (but beautiful) new ballrooms at the Convention Center, but mostly because of industry divergences. There is no longer a s... » read more

SoC Integration Mistakes
By Ed Sperling - 10 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

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