Overview: Ultra Ethernet’s Design and Architectural Advancements (ETH Zurich, Broadcom, HPE et al.)


A new technical paper titled "Ultra Ethernet's Design Principles and Architectural Innovations" was published by researchers at ETH Zurich, Broadcom, Hewlett Packard Enterprise, OpenAI, Intel, Microsoft, AMD and Cisco. Abstract "The recently released Ultra Ethernet (UE) 1.0 specification defines a transformative High-Performance Ethernet standard for future Artificial Intelligence (AI) and ... » read more

Chip Industry Technical Paper Roundup: August 19


New technical papers recently added to Semiconductor Engineering’s library: [table id=465 /] Find more semiconductor research papers here. » read more

Low-Latency Interconnect for Close-Coupled On-Chip Communication With Error Correction Code Protection (ETH Zurich)


A new technical paper titled "relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication" was published by researchers at ETH Zurich. Excerpt "On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care in radiation-heavy environments, as any soft... » read more

Chip Industry Technical Paper Roundup: July 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=456 /] Find more semiconductor research papers here.   » read more

Analysis of RISC-V CPU Fuzzers via Automatic Bug Injection (ETH Zurich)


A new technical paper titled "Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection" was published by researchers at ETH Zurich. Abstract "Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and ... » read more

Chip Industry Technical Paper Roundup: July 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=445 /] Find more semiconductor research papers here. » read more

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich et al.)


A technical paper titled "Data-driven power modeling and monitoring via hardware performance counter tracking" was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract "Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an afforda... » read more

Research Bits: June 24


In-sensor visual processing Researchers from the University of Massachusetts Amherst created silicon-based in-sensor visual processing arrays that can both capture and process visual data in the analog domain to reduce the latency between sensing and identification. The team created two integrated arrays of gate-tunable silicon photodetectors that share bipolar analog output and low-power o... » read more

Chip Industry Week in Review


Texas Instruments will invest more than $60 billion to build and expand seven semiconductor fabs in Texas and Utah, supporting more than 60,000 U.S. jobs. Chinese automakers — including SAIC Motor, Changan, Great Wall Motor, BYD, Li Auto and Geely — are aiming to launch new models with 100% homemade chips, some as early as 2026, reports Nikkei Asia. Marvell introduced 2nm custom SRAM ... » read more

Chip Industry Technical Paper Roundup: June 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=438 /] Find more semiconductor research papers here. » read more

← Older posts Newer posts →