Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEPTEC.
(L-R) Chenglin Liu, John Hunt, Eric Tosaya, Juan Rey
SE: How has advanced packaging impacted the design chain?
Rey: From my perspective, advanced packaging includes anything that is 2.5D or 3D. Using that as a direction, from our point of view there have been several flow-related impacts for the design community. These technologies enable you to disaggregate monolithic design because you can think of an interconnect with characteristics outside of the chip, that are very similar to the characteristics on the inside of the chip. But now you have the ability to integrate different technologies, which ideally are optimized for memory or RF or power, and with that come new challenges. The first challenge is that because you have very large, heterogeneous characteristics, you have to be aware of that. We have modify our tools to deal with multiple technologies. That invites physical verification such as design rule checking, layout versus schematic. Now you have to go through an interposer or some type of interconnect technology. In this case, it affects the interconnected characteristics of the system and how those may impact each other. It affects the design for manufacturability characteristics. So there are several things that have to be modified in the tools and in the flow so that we can facilitate this task.
Liu: At Marvell we have been doing this for quite a long time, but there’s a difference in the order involved. We’re modifying the design flow right now. So far we did things on the package, in the package, using conventional software providers. We put different kinds of die on the substrate along with the package.
Tosaya: eSilicon has done quite a few 2.5D implementations. What we found is that the complexity has increased significantly. We were basing our designs initially around an Excel spreadsheet with all of the interconnects described, from chip to substrate, from interposer to substrate, substrate to board, substrate to test board. It just becomes very unwieldy. There is a lot of manual integration, piecemeal checking, and a lot of risk for making mistakes. So internally over the past year there has been an effort to create a much more automated design flow based on commercially available tools. This is meant to remove as much of the manual part as possible and automate the checking. That’s been a necessity from the increased sophistication of the design, going from one ASIC with one HBM to what is now four HBMs and one big ASIC and with many SerDes on it.
Hunt: Fan-out is our major focus. That’s also wafer-level chip-scale packaging. The original fan-out, the first one in production, was eWLB (embedded wafer-level ball grid array) from Infineon, which was a low-density product. It could be designed the way we design wafer-level CSPs (chip-scale packages). But then in 2016, we brought out the FoCoS (fan-out chip on substrate), which is a substitute for an interposer solution. With the evolution of that density, our designers who were not skilled in that type of technology were able to design complex packages. The routing has to be designed manually. ASE has been working with suppliers to automate as much of this as we can, but it’s forcing us to evolve our whole design infrastructure to be able to accommodate the complexity we’re seeing. Another problem we’re seeing is that all of this is continually evolving. We’re constantly developing new capabilities in materials and new processes and new dimensional capabilities, which form the basis of how we put together the features. So our design requirements are changing constantly, too. All of that is evolving very quickly, and it can be painful.
SE: So who’s using advanced packaging today and why, and will that change over time?
Tosaya: We’ve done designs on AI and design for telecomm and data switch equipment. It’s really driven, at least for Tier 1 customers, by high performance. They want the maximum bandwidth, so we’re meeting their performance requirements.
SE: This is in addition to 7nm development, or is it at an older node?
Tosaya: We’ve been doing this on 16/14nm. We have a 7nm platform based on TSMC technology. But the cost of 7nm makes our customers think carefully about how to apply that technology, and what is the right partitioning to get the right balance of cost and performance. Package integration is what’s allowing them to achieve a better solution than just automatically going down the old path, which is to shove everything onto silicon that you can. That doesn’t make sense in terms of cost and performance.
Hunt: Our fan-outs were introduced for server applications. So it was heterogeneous integration, where the customer partitioned the die between two technology nodes. We’re also working on homogeneous integration, where they partition the same die at the same node. But it’s not just partitioning the silicon. It’s also putting in different technology. For SiP applications, we’re getting more complicated fan-out structures where the customers are asking to integrate filters and to put passives right into the fan-out structure itself. All of this isn’t the same complexity as an interposer solution, but it’s more complex than what we’ve used in the past.
Rey: For mobility and high-performance computing, we are seeing an interest growing in the automotive industry, and also for machine learning types of applications and AI in general.
Liu: This varies by application. We’re seeing high-bandwidth memory and 7nm are too expensive. The die size is too big. It’s reticle size. You have no choice but to resize the die for your application. It’s more of a modular design.
SE: How much do these packages cost versus ASICs and FPGAs?
Hunt: Fan-out solutions, where they are able to substitute for an interposer solution, we can do 2μ lines and spaces. We do four RDL layers, a UBM (under bump metallization) layer plus a copper pillar. So we do six metal layers. Our yields are 98.5%. So we’re getting very good yield, and the cost is significantly lower than an interposer-based solution. But if we have to go down to 1 micron line and space or less, right now that’s not an optimal solution. Still, the performance we see on the fan-out is better electrically and thermally than an interposer solution. Our RDL is thicker than the traces on an interposer, and our vias are larger. They aren’t as deep. So we see better electrical performance where we can use a fan-out, and it’s much thinner. The interposer is 100 microns. A fan-out is only about 25 microns. Cost-wise, we can compete in those applications where it’s suitable.
Liu: From what we see on the cost, it’s still too high for all products. We dealing with storage and networking and processors—basically infrastructure for a company. But the cost is quite high.
Tosaya: One customer that we have right now, rather than doing an extremely large ASIC at the reticle limit, they specifically chose to go with a smaller chip. They have two versions of it. One is a single-chip BGA. The high performance version of that product uses two of the sameASICs, no HBM, on an interposer in a larger substrate. They found out that is an effective cost-performance solution compared with two single BGAs. That tells you there’s value there.
Rey: We can’t comment on cost because our market is EDA. But we have to develop and support pretty much every type of technology developed in 2.5D and 3D, because clearly our customer base has been doing some level of this. Each one of them has to look at cost, performance and area requirements, and for some of them it makes sense.
Related Stories
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply