Making 2.5D, Fan-Outs Cheaper

Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.


Now that it has been shown to work, the race is on to make advanced packaging more affordable.

While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it.

At the center of this push are three main issues, all of which have a major impact on cost:

Yield. How does the semiconductor industry add the same level of confidence that a design will yield sufficiently using new packaging?
Process. Can it leverage existing process technology that has been proven and refined over the past 50 years, and with at least the same 30% power/performance improvement chipmakers and their customers have come to expect.
Materials. Can this be done utilizing existing materials that are in plentiful supply, possibly in conjunction with exotic compounds that can improve electron mobility or withstand greater temperature extremes.

There are numerous other issues that can influence cost, and which collectively can result in huge fluctuations from one design to the next. Among those are floor planning, IP compatibility and characterization, proper allocation of resources such as memories, software design, physical effects such as heat, and the ability to build these systems quickly enough to hit market windows. But without sufficient and proven yield, the ability to leverage existing process technology, and the continued reliance of silicon and copper, none of those other factors matter.

Until the 22nm, predictability on all of those fronts was almost guaranteed. Beyond that, as multiple patterning and 3D transistors enter the picture, it becomes economically harder to justify putting everything on a single die.

“With a 7nm design, the lifetime revenue of a chip needs to be about $3 billion,” said David McCann, vice president of packaging R&D and operations at GlobalFoundries. “Moore’s Law is falling down. The cost of meeting Moore’s Law is increasing and the demand for performance is increasing. A portion of the roadmap now requires multi-die modules.”

For a chip developed at 7nm, the development tools cost about $5 billion. Add to that another $500 million to bring a chip to production, $100 million for mask tools, and another $5 million for a mask set.

To make matters worse, analog doesn’t scale, memory scaling is lagging behind the rest of the SoC, and devices in general are slowing down because of very long interconnects. While these issues can be solved through extensive and expensive engineering, the clear direction is a multi-die solution, said McCann, speaking at the Microelectronics Packaging and Test Engineering Council meeting earlier this week in San Jose. “That will provide a significant increase in bandwidth per second and a decrease in picajoules per bit.”

Different approaches
McCann’s observation that multi-chip packaging will be required is gaining support across a wide swath of the semiconductor industry. Large processor companies such as Intel, Xilinx, AMD and IBM, as well as all of the major commercial foundries, IP vendors such as ARM, and many industry organizations are now backing advanced packaging. So are big equipment makers and test companies, and system design houses such as eSilicon and Open-Silicon.

But at least so far, there is no clear agreement about which approach is best. Is it 2.5D or 2.1D, using an organic or organic laminate interposer? Or is it some variation of a fan-out or a full 3D-IC?

Fan-outs have a running start in the high-volume world, given that Apple has used TSMC’s InFO approach in the iPhone 7. But even with fan-outs there are a number of options, including chip first die up or die down, where the package is built around the chip, and chip last, where a more standardized chip is added into a packaging. There also are options for wafer-level bonding, package-on-package and multiple versions of system-in-package.

“Fan-out certainly plays a big role as an enabler of a range of solutions, said Eelco Bergman, senior director of sales and business development at ASE Group. “If you look at where the money is, it’s content and services. The way to achieve that is with the operating system and software, and to have a hardware gateway to these. The more overlap, the more you can build an ecosystem to lock in the user, which is what all the big systems companies are doing today. Hardware is a means to an end, and that puts pressure on us to decrease the cost. Heterogeneous integration provides an alternative.”

It also provides a way to speed up time to market and to improve re-use. DARPA, for one, experimented with monolithic 3D and epitaxial printing before settling on a chiplet approach. In effect, the agency deconstructs an SoC down into its most basic components using a series of chiplets.

“For any flow, we can show the benefit of heterogeneous integration,” said Daniel Green, program manager at DARPA. “We could swap out different technologies and repurpose circuits for different frequencies. That also helps with reuse of IP because you don’t have to design it again and again.”

DARPA has developed what it calls a Common Heterogeneous Integration and IP Reuse Strategies Program (CHIPS), based on the concept of a library of parts that can work together. That library ultimately will include DARPA’s parts plus commercial parts. Green said the big challenge, and one that needs to be solved by the industry, is to create interface standards for these chiplets based on two metrics, gigabits/second/millimeter and energy/bit.

“There is a gap right now,” he said. “The CHIPS challenge is a usable interface standard.”

Other standards groups are working on this problem, as well. William Chen, a fellow at ASE, said there currently are 19 technical working groups involved in the Heterogeneous Integration Roadmap (HIR), which is being driven by SEMI, and three IEEE groups, the Photonics Society, Electron Devices Society (EDS) and the Components, Packaging and Manufacturing Technology Society (CPMT). HIR’s stated is to develop solutions that can span everything from smart devices to the cloud. Chen said the first roadmap will be issued on March 31, 2017.

Universities are stepping in, too. Subramanian Iyer, professor of electrical engineering at UCLA, believes the solution is mounting hard IP on a board. “This is comparable to final metal on a chip,” he said. “You can eliminate most of the SerDes except for very long links. The primary benefit is a 100X decrease in power and you get multi-terabit connections.”

UCLA’s approach, like DARPA’s, relies on breaking everything down into pieces. Iyer refers to them as dielets, and says they need to be less than 3mm x 3mm and highly standardized. “With greater standardization, you can move the die closer to each other and you can get extremely low power per bit and decrease latency to a few picoseconds.”

These kinds of metrics are just beginning to surface as more advanced packaging is used commercially. DARPA’s Green said that a 130nm system in package with silicon phosphide showed equivalent power/performance as a 28nm planar chip, which represents a five-node improvement. “This isn’t more than Moore. It’s more of Moore.”

Integrating new materials
When the idea of putting multiple die into a package began getting a second look, prior to the commercial rollout of finFETs at 16nm/14n, one of the big arguments in favor of this approach was that it could be used to combine multiple process technologies. As a result, digital logic could be developed at 16/14nm, for example, while analog power supplies or sensors could be developed at 180nm or larger.

Initial implementations of advanced packaging utilized the high-speed interconnects between various components, but so far they all have been done using the same process technology. So a 40nm 2.5D chip would include all components developed at a 40nm process. Chen said that is beginning to change as advanced packaging becomes more widespread.

But there are other advantages to this approach that appear to be new, as well. Rather than just mixing up process nodes, these new packages could house different materials, such as gallium arsenide and indium arsenide and indium gallium arsenide, all of which are used as light sources for silicon photonics. The problem with these materials is that they are difficult to work with using conventional silicon processes, but as chiplets or dielets they can be much more easily integrated into packages or mounted to a board.

This is particularly useful in high-performance applications. It also is useful in markets such as mil/aero, automotive and industrial, where key parts of a device need to be able to withstand conditions such as heat, radiation, and electromagnetic interference.

Remaining problems
One area that continues to be problematic is test. While the testing methodology itself has been worked out even for monolithic 3D-IC, questions remain about the impact of test on known good die in a package.

GlobalFoundries’ McCann contends that all that should be tested at the module level is whether there was damage caused by putting a chip into a module and whether the interconnect was added properly.

“There should be a boundary test for all interconnect testing,” he said. “This is where DFT expertise is really important.” He noted that the real problem often isn’t a test issue. It’s a yield management issue.

That puts some of the onus back on the design side. Brandon Wang, group director at Cadence, said one of the key challenges is partitioning. “It’s a question of how you partition the design so the dies are similar in size for wafer-level packaging,” he said. “There also is a question of how you do clock-tree synthesis when it may cut across multiple dies with different processes. And there are questions about how you do physical synthesis that generates a 3D-aware netlist. What king of granularity do you need for floor planning and place and route? And do you do DFT with all of these pieces together or separately?”

So far, there are no clear answers to those questions. But given the amount of attention being paid to advanced packaging, the first large-scale commercial rollouts from companies such as Apple, Huawei, Cisco, AMD, IBM and others, those problems will be solved within the next few years. And with that, hopefully there will be enough research to begin adding economies of scale.

“This is really going to be about cost,” said McCann.

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  • Dev Gupta

    Integration solutions developed at Foundries or provided by OSATs are sub optimal because unlike IDMs they do not have the comprehensive knowledge of Systems needed to initiate effective trade offs. For many applications Silicon Interposers with Dual Damascene metallization are an overkill.To reduce the cost of 2.5 d interposers Intel already embeds high density Si inserts ( bridges ) onto Organic substrates. Hopefully the OSATS will soon follow.

    • Ed Sperling

      Dev, you’re talking about the Embedded Multi-die Interconnect Bridge, or is there something else in there, as well?