AI, Product Lifecycle Management, Market Dynamics: Q&A With Jay Vleeschhouwer Of Griffin Securities 

In the world of EDA, Jay Vleeschhouwer, managing director of software research at Griffin Securities, needs no introduction. His presentation on the State of EDA is standing room only at the yearly Design Automation Conference (DAC).

He recently agreed to a discussion with me where we talked about AI and EDA, an interesting development with product lifecycle management and global dynamics affecting EDA. A condensed version of our talk follows.

Bob Smith: Is EDA effectively leveraging AI?

Vleeschhouwer: Within the overall context of Engineering Software, AI and ML are further along in terms of availability and production deployment in the EDA part of the industry as compared with the other Engineering Software segments.

When you consider the presentations and testimonials at a Cadence or Synopsys event, this technology is being used in production at scale by major customers.

EDA is meticulously dependent on advances in productivity in multiple, highly measurable and definable areas. AI/ML are naturally usable, provided that there are attributable effects. In other words, this thing called ML, however branded by the vendors, is in fact having demonstrable effects on the critical metrics important in EDA – such as quality of results and PPA.

In other parts of Engineering Software, metrics and productivity requirements and objectives are not quite as detailed as EDA precisely because of the differences in what’s being produced. Again, in EDA if AI/ML tools can have significant attributable results, then that’s going to result in adoption and growth in this industry.

ML has to do more specifically with optimization because so much of what EDA strives for is optimization. Whereas AI is applied for interactive exploration. That’s interesting and important—where the exploration part helps define and narrow down options and outcomes. The ML part allows more precise and meticulous convergence on a solution meeting highly defined objectives or parameters, i.e. the optimization part.

To build upon that, we’ve also been observing the rise of agentic AI, that is the use of agents. That is raising questions about the right or optimal number of agents that a software vendor should introduce. I don’t know the answer. I think it’s a question as to how many of these agents are needed.

Particularly in the case of EDA, because of the dozens of types of applications and functions all the way from RTL through tape-out, does that mean a similar or equivalent number of agents, that is, dozens of agents, along the way? Then another term that’s come up not just from EDA but more broadly is the term orchestration, as in orchestrating the use of the agents and how they work and managing that whole process.

That is an interesting question as well. How do you manage a process of agents and meet new ways of interacting with the software and the design and converging on a desired or optimal solution? When do you stop using the agents? If agenting is a word, when do you stop agenting?

With AI/ML, there’s still a long way to go.

Smith: You mention product lifecycle management in some of your reports. Can you explain the concept?

Vleeschhouwer: Yes, lifecycle management, in other words, managing the whole process, is an important issue.

It’s remarkable how little it’s been employed as a set of technologies in EDA. I’m referring to what in the industrial side has been called PLM, product lifecycle management. We are beginning to hear more recently about silicon lifecycle management. Siemens EDA has been referring to this more explicitly. For EDA to continue to succeed, the availability and implementation of this process, known as Silicon Lifecycle Management or SLM, is required.

An earlier use of SLM by Synopsys had more to do with embedding sensors in devices. This is a similar but broader term having to do with the overall management of the process. Another example is the recent announcement about Siemens’ work with Perforce.

All else being equal, particularly in the context of making convergence work, lifecycle management and process management are going to be an increasingly important technical requirement and deliverable on the part of the vendors. One of the terms related to that is traceability, a term borrowed from the industrial world.

Traceability has to do with managing results of design and simulation processes, attribution, and it all ties into having a suitable data management platform. The EDA vendor’s ability to have an underlying platform will become increasingly critical in addition to the day-to-day competition just around the tools and the apps themselves.

One of the reasons that, a few years ago when Cadence started its intelligent system design strategy, or ISD, we advocated for its having this kind of capability. If Cadence means to succeed in ISD, its multi-physics and convergence, then it necessitated having some capability of this kind.

That in turn is what led them to have a relationship with the French software company Dassault Systèmes, because Dassault has one of the principal brands for doing that kind of process and data management – in addition to which Dassault needed some way to gain access into the electronics market in pursuit of its strategy.

One of the things that stood out and rose to the top of the list of executables was what we’ll call for now silicon lifecycle management. This is something that will be interesting to continue to hear about from Siemens, Synopsys or Synopsys plus Ansys, and Cadence.

In the case of Synopsys and Ansys, Ansys brings to the party some existing capability of that kind. For the last number of years, Ansys has been offering something known as Simulation Process and Data Management or SPDM, under the brand name Minerva. This has been apart from the pure solver business that Ansys has, one of Ansys’ most interesting and important strategic initiatives, among a couple of others prior to the Synopsys absorption. They will bring to this combined company some capabilities that may potentially give Synopsys a good starting point for this new requirement.

Smith: How do you see global dynamics affecting the market, specifically the changes at Intel and the May directive stopping sales of EDA tools to China that’s since been lifted?

Vleeschhouwer: With Intel, that’s been a question now for a year or more, certainly in the last couple of quarters. We published a couple of reports about that and then on the export restrictions in the last few weeks. I put out a piece earlier in the month, as we’ve been doing now each quarter, with our updated compilation of open engineering jobs at Intel and Nvidia.

What we’ve seen with Intel through the first quarter of this year is four consecutive sequential declines of total R&D. That has resulted as of the first quarter in Nvidia’s having become the largest spender in terms of total R&D. Not yet in terms of EDA, but as of the most recent quarter, Nvidia’s R&D surpassed that of Intel. That was foreseeable. That was the way the trajectory looked, though we think that Nvidia’s EDA spending, probably approaching the mid-nine figures, is not quite at Intel’s level yet.

In terms of our report, we showed that open engineering positions at Intel, specifically with relevance to EDA, have been substantially constrained the last number of quarters, particularly as of the end of Q2. Clearly, there is substantial constraint going on at Intel. By contrast, the numbers for Nvidia showed a reasonably large increase from the first quarter to the second quarter in terms of the number of engineering openings of specific relevance to EDA.

It was not a record. In fact, the record was for Nvidia at least a couple of years ago. It’s clear that they are broadly looking to hire in many functional and product areas that are relevant to EDA and to each of the vendors. We also calculated in a recent report that the trailing 12-month revenues of Intel to Synopsys for the most recent period ended Q1 were less than the revenues to Synopsys from Intel in Synopsys’ fiscal ’24.

The intra-year calculated number is based on our own estimation. That number, while still substantial at three quarters of a billion dollars, seems to have been somewhat smaller than the number for the fiscal year, which would likely have been attributable to the variance in one or both of hardware and IP. Both of those can be quite variable, not just with Intel but with most customers. Much of the revenue for both, particularly hardware, is upfront, hence the variability.

Even with that, Intel spending remains the largest in the industry. If there were to be structural changes in terms of employment and EDA capacity – they are committed to a multi-year contract – there are numerous similar openings elsewhere in the industry, including Nvidia, Arm, AMD, Qualcomm and Broadcom. If there were to be reductions at Intel, there’s more than enough capacity need elsewhere in the industry to absorb that. Again, it remains to be seen what the structural changes are in terms of the overall EDA deployment at Intel.

With regard to restrictions, shortly after the restrictions were announced, we published a detailed report on EDA in China to give investors a picture of the scope of the revenues in China for EDA software and IP, what the revenues were for individual vendors, the market shares and so forth, to give them some context.

When it was announced a week or so ago that the restrictions were in fact rescinded, we put out a brief note about that. What remains to be seen is whether those four or five weeks of restriction and suspension can be recouped in terms of revenue. Or if that business was gone and no longer reportable for that period. Or whether there’s some way to reinstate it by the vendors.

Jay Vleeschhouwer, managing director of software research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf 

A webinar about changes to the U.S. import/export regulations is in the planning stages within the ESD Alliance and SEMI. Details will be announced soon.

The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz.